Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. - Kodai Ueyoshi; Takao Marukame; Tetsuya Asai; Masato Motomura; Alexandre Schmid (ISCAS, 2016)

FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. - Kentaro Orimo; Kota Ando; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (ReConFig, 2016)

Accelerating deep learning by binarized hardware. - Shinya Takamaeda-Yamazaki; Kodai Ueyoshi; Kota Ando; Ryota Uematsu; Kazutoshi Hirose; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (APSIPA, 2017)

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. - Kazutoshi Hirose; Ryota Uematsu; Kota Ando; Kentaro Orimo; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (CANDAR, 2017)

Exploring optimized accelerator design for binarized convolutional neural networks. - Kodai Ueyoshi; Kota Ando; Kentaro Orimo; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (IJCNN, 2017)

Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. - Kodai Ueyoshi; Takao Marukame; Tetsuya Asai; Masato Motomura; Alexandre Schmid (ISCAS, 2017)

In-memory area-efficient signal streaming processor design for binary neural networks. - Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Kota Ando; Kodai Ueyoshi; Kazutoshi Hirose; Kentaro Orimo; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (MWSCAS, 2017)

Quantization Error-Based Regularization in Neural Networks. - Kazutoshi Hirose; Kota Ando; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (SGAI Conf., 2017)

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. - Takao Marukame; Kodai Ueyoshi; Tetsuya Asai; Masato Motomura; Alexandre Schmid; Masamichi Suzuki; Yusuke Higashi; Yuichiro Mitani (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. - Kota Ando; Kodai Ueyoshi; Yuka Oba; Kazutoshi Hirose; Ryota Uematsu; Takumi Kudo; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (FPT, 2018)

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Junichiro Kadomoto; Tomoki Miyata; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (ISSCC, 2018)

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. - Takumi Kudo; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Ryota Uematsu; Yuka Oba; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (MCSoC, 2018)

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. - Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2018)

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. - Kota Ando; Kodai Ueyoshi; Yuka Oba; Kazutoshi Hirose; Ryota Uematsu; Takumi Kudo; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (IEICE Trans. Inf. Syst., 2019)

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2019)

A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. - Kota Shiba; Tatsuo Omori; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Masato Motomura; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2020)

A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. - Kota Shiba; Tatsuo Omori; Kodai Ueyoshi; Shinya Takamaeda-Yamazaki; Masato Motomura; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. - Kodai Ueyoshi; Ioannis A. Papistas; Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Man Shi; Qilin Zheng; Juan Sebastian Piedrahita Giraldo; Peter Vrancx; Jonas Doevenspeck; Debjyoti Bhattacharjee; Stefan Cosemans; et al. (ISSCC, 2022)

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. - Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Kodai Ueyoshi; Ioannis A. Papistas; Man Shi; Qilin Zheng; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest; Marian Verhelst (IEEE J. Solid State Circuits, 2023)