Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process. - Kodai Yamada; Haruki Maruoka; Jun Furuta; Kazutoshi Kobayashi (IRPS, 2018)

Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process. - Mitsunori Ebara; Kodai Yamada; Jun Furuta; Kazutoshi Kobayashi (IOLTS, 2019)

Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process. - Jun Furuta; Yuto Tsukita; Kodai Yamada; Mitsunori Ebara; Kentaro Kojima; Kazutoshi Kobayashi (IRPS, 2019)

An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer. - Kentaro Kojima; Kodai Yamada; Jun Furuta; Kazutoshi Kobayashi (IRPS, 2019)

Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters. - Kentaro Kojima; Kodai Yamada; Jun Furuta; Kazutoshi Kobayashi (IEICE Trans. Electron., 2020)

A Deep Learning Technique for Electricity Price Forecasting in Consideration of Spikes. - Kodai Yamada; Hiroyuki Mori (TENCON, 2021)