DVTS: Design Verification Techniques for Functional Simulation. - Kohei Fukuoka; Ken Ohga; Atsushi Sugiyama; Satoshi Takemura (ITC, 1986)

Mixed body bias techniques with fixed Vt and Ids generation circuits. - Masaya Sumita; Shiro Sakiyama; Masayoshi Kinoshita; Yuta Araki; Yuichiro Ikeda; Kohei Fukuoka (IEEE J. Solid State Circuits, 2005)