Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications. - Kohei Onizuka; Hiroshi Kawaguchi 001; Makoto Takamiya; Tadahiro Kuroda; Takayasu Sakurai (CICC, 2006)

$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time. - Kohei Onizuka; Hiroshi Kawaguchi 001; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2006)

Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs. - Kohei Onizuka; Kenichi Inagaki; Hiroshi Kawaguchi 001; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2007)

A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller. - Kohei Onizuka; Hiroaki Ishihara; Masahiro Hosoya; Shigehito Saigusa; Osamu Watanabe 003; Shoji Otaka (CICC, 2011)

A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier. - Shouhei Kousai; Kohei Onizuka; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (ISSCC, 2012)

A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique. - Kohei Onizuka; Shigehito Saigusa; Shoji Otaka (VLSIC, 2012)

A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier. - Shouhei Kousai; Kohei Onizuka; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (IEEE J. Solid State Circuits, 2012)

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion. - Kohei Onizuka; Hiroaki Ishihara; Masahiro Hosoya; Shigehito Saigusa; Osamu Watanabe 003; Shoji Otaka (IEEE J. Solid State Circuits, 2012)

A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications. - Kohei Onizuka; Shigehito Saigusa; Shoji Otaka (ISSCC, 2013)

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations. - Shouhei Kousai; Kohei Onizuka; Song Hu 003; Hua Wang 006; Ali Hajimiri (CICC, 2014)

3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier. - Shouhei Kousai; Kohei Onizuka; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (ISSCC, 2014)

Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier. - Shouhei Kousai; Kohei Onizuka; Junji Wadatsumi; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (IEEE J. Solid State Circuits, 2014)

Head ballistocardiogram based on wireless multi-location sensors. - Kohei Onizuka; Charles G. Sodini (EMBC, 2015)

Session 2 overview: Power amplifiers. - Kohei Onizuka; Abbas Komijani; Piet Wambacq (ISSCC, 2017)

F2: High-performance frequency generation for wireless and wireline systems. - Jiayoon Ru; Kohei Onizuka; Pavan Kumar Hanumolu; Roberto Nonis; Howard C. Luong; Jan Craninckx (ISSCC, 2017)

Efficient energy beamforming for multi-device microwave wireless power transfer under Tx/Rx power constraints. - Kentaro Murata; Kohei Onizuka; Toshiya Mitomo; Makoto Higaki; Kentaro Taniguchi; Ryoko Matsuo; Tsuguhide Aoki (PIMRC, 2017)

A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. - Yosuke Toyama; Kentaro Yoshioka; Koichiro Ban; Akihide Sai; Kohei Onizuka (A-SSCC, 2018)

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer. - Shusuke Kawai; Hiromitsu Aoyama; Rui Ito; Yutaka Shimizu; Mitsuyuki Ashida; Asuka Maki; Tomohiko Takeuchi; Hiroyuki Kobayashi; Go Urakawa; Hiroaki Hoshino; Shigehito Saigusa; Kazushi Koyama; et al. (ISSCC, 2018)

PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators. - Kentaro Yoshioka; Yosuke Toyama; Koichiro Ban; Daisuke Yashima; Shigeru Maya; Akihide Sai; Kohei Onizuka (VLSI Circuits, 2018)

An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer. - Shusuke Kawai; Rui Ito; Kengo Nakata; Yutaka Shimizu; Motoki Nagata; Tomohiko Takeuchi; Hiroyuki Kobayashi; Katsuyuki Ikeuchi; Takayuki Kato; Yosuke Hagiwara; Yuki Fujimura; Kentaro Yoshioka; et al. (IEEE J. Solid State Circuits, 2018)

A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs. - Shusuke Kawai; Takeshi Ueno; Kohei Onizuka (ISSCC, 2019)

An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators. - Yosuke Toyama; Kentaro Yoshioka; Koichiro Ban; Shigeru Maya; Akihide Sai; Kohei Onizuka (IEEE J. Solid State Circuits, 2019)

18.8 A Fully-Generic-Process Galvanic Isolator for Gate Driver with 123mW 23% Power Transfer and Full-Triplex 21/14/0.5Mb/s Bidirectional Communication Utilizing Reference-Free Dual-Modulation FSK. - Hiroaki Ishihara; Kohei Onizuka (ISSCC, 2020)

18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics. - Satoshi Takaya; Hiroaki Ishihara; Kohei Onizuka (ISSCC, 2020)

A 5.7GHz RF Wireless Power Transfer Receiver Using 84.5% Efficiency 12V SIDO Buck-Boost DC-DC Converter with Internal Power Supply Mode. - Tomohiro Higuchi; Dai Suzuki; Ryo Ishida; Yasuaki Isshiki; Kazuki Arai; Kohei Onizuka; Kousuke Miyaji (A-SSCC, 2021)

A Tile-based 8×8 Triangular Grid Array Beamformer for 5.7 GHz Microwave Power Transmission. - Kazuki Arai; Kaili Wang; Toshiya Mitomo; Makoto Higaki; Kohei Onizuka (RWS, 2021)

An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs. - Shusuke Kawai; Takeshi Ueno; Hiroki Ishikuro; Kohei Onizuka (IEEE J. Solid State Circuits, 2023)