A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. - Gil-Cho Ahn; Dong-Young Chang; Matthew E. Brown; Naoto Ozaki; Hiroshi Youra; Ken Yamamura; Koichi Hamashita; Kaoru Takasuka; Gábor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2005)

A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR. - Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes (ISSCC, 2008)

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR. - Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes (IEEE J. Solid State Circuits, 2008)

A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator. - Junpei Kamiishi; Yun-Shiang Shu; Koji Tomioka; Koichi Hamashita; Bang-Sup Song (CICC, 2009)

A Fifth-Order Gm-C Continuous-Time ΔΣ Modulator With Process-Insensitive Input Linear Range. - Yusuke Aiba; Koji Tomioka; Yuta Nakashima; Koichi Hamashita; Bang-Sup Song (IEEE J. Solid State Circuits, 2009)

A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver. - Kyehyung Lee; Qingdong Meng; Tetsuro Sugimoto; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Un-Ku Moon; Gabor C. Temes (IEEE J. Solid State Circuits, 2009)

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback. - Naga Sasidhar; Youn-Jae Kook; Seiji Takeuchi; Koichi Hamashita; Kaoru Takasuka; Pavan Kumar Hanumolu; Un-Ku Moon (IEEE J. Solid State Circuits, 2009)

A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer. - Jeongseok Chae; Sanghyeon Lee; Mitsuru Aniya; Seiji Takeuchi; Koichi Hamashita; Pavan Kumar Hanumolu; Gabor C. Temes (CICC, 2010)

An Enhanced Dual-Path DeltaSigma A/D Converter. - Yoshio Nishida; Koichi Hamashita; Gabor C. Temes (IEICE Trans. Electron., 2010)

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC. - Omid Rajaee; Tawfiq Musah; Nima Maghari; Seiji Takeuchi; Mitsuru Aniya; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2010)

LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators. - Yun-Shiang Shu; Junpei Kamiishi; Koji Tomioka; Koichi Hamashita; Bang-Sup Song (IEEE J. Solid State Circuits, 2010)

A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application. - Sanghyeon Lee; Jeongseok Chae; Mitsuru Aniya; Seiji Takeuchi; Koichi Hamashita; Pavan Kumar Hanumolu; Gabor C. Temes (CICC, 2011)

Binary Access Memory: An optimized lookup table for successive approximation applications. - Benjamin P. Hershberg; Skyler Weaver; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (ISCAS, 2011)

Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer. - Omid Rajaee; Seiji Takeuchi; Mitsuru Aniya; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2011)

Direct-digital modulation (DIDIMO) transmitter with -156dBc/Hz Rx-band noise using FIR structure. - Shuichi Fukuda; Shinji Miya; Miho Io; Koichi Hamashita; Bram Nauta (ESSCIRC, 2012)

A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers. - Benjamin P. Hershberg; Skyler Weaver; Kazuki Sobue; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (VLSIC, 2012)

Ring Amplifiers for Switched Capacitor Circuits. - Benjamin P. Hershberg; Skyler Weaver; Kazuki Sobue; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2012)

Parallel gain enhancement technique for switched-capacitor circuits. - Hariprasath Venkatram; Benjamin P. Hershberg; Taehwan Oh; Manideep Gande; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (CICC, 2013)

Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs. - Yuichi Miyahara; Mitsuhiro Sano; Kazuo Koyama; Toshikazu Suzuki; Koichi Hamashita; Bang-Sup Song (ISSCC, 2013)

A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier. - Hariprasath Venkatram; Taehwan Oh; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (VLSIC, 2014)

A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity. - Yuichi Miyahara; Mitsuhiro Sano; Kazuo Koyama; Toshikazu Suzuki; Koichi Hamashita; Bang-Sup Song (IEEE J. Solid State Circuits, 2014)

A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays. - Xin Meng; Jinzhou Cao; Tao He 001; Yi Zhang 023; Gabor C. Temes; Mitsuru Aniya; Kazuki Sobue; Koichi Hamashita (ESSCIRC, 2015)

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers. - Hyuk Sun; Jason Muhlestein; Spencer Leuenberger; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (A-SSCC, 2016)

A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (ISCAS, 2016)

A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Tejasvi Anand; Un-Ku Moon (CICC, 2017)

A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Kazuki Sobue; Koichi Hamashita; Gabor C. Temes (CICC, 2017)

A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR. - Takato Katayama; Shiko Miyashita; Kazuki Sobue; Koichi Hamashita (VLSI Circuits, 2018)

An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications. - Mahmoud Sadollahi; Koichi Hamashita; Kazuki Sobue; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Oversampling Stochastic ADC Using VCO-Based Quantizers. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier. - Ahmed ElShater; Calvin Yoji Lee; Praveen Kumar Venkatachala; Jason Muhlestein; Spencer Leuenberger; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (ISSCC, 2019)

A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier. - Ahmed ElShater; Praveen Kumar Venkatachala; Calvin Yoji Lee; Jason Muhlestein; Spencer Leuenberger; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2019)

A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry. - Shota Konno; Yuichi Miyahara; Kazuki Sobue; Koichi Hamashita (A-SSCC, 2020)

A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Tejasvi Anand; Un-Ku Moon (IEEE J. Solid State Circuits, 2020)

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. - Yanchao Wang 001; Siladitya Dey 002; Tao He 001; Lukang Shi; Jiawei Zheng; Manjunath Kareppagoudr; Yi Zhang 023; Kazuki Sobue; Koichi Hamashita; Koji Tomioka; Gabor C. Temes (A-SSCC, 2021)