A hardware/software partitioning algorithm for SIMD processor cores. - Koichi Tachikake; Nozomu Togawa; Yuichiro Miyaoka; Jinku Choi; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2003)

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Instruction set and functional unit synthesis for SIMD processor cores. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2004)

A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Inf. Syst., 2005)