A 5-ns 1-Mb ECL BiCMOS SRAM. - Masahide Takada; Kazuyuki Nakamura; Toshio Takeshima; Koichiro Furuta; Tohru Yamazaki; Kiyotaka Imai; Susumu Ohi; Yumi Sekine; Yukio Minato; Hisamitsu Kimuto (IEEE J. Solid State Circuits, 1990)

A 30-ns 256-Mb DRAM with a multidivided array structure. - Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; Tatsuya Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; et al. (IEEE J. Solid State Circuits, 1993)

A GHz MOS adaptive pipeline technique using MOS current-mode logic. - Masayuki Mizuno; Masakazu Yamashina; Koichiro Furuta; Hiroyuki Igura; Hitoshi Abiko; Kazuhiro Okabe; Atsuki Ono; Hachiro Yamada (IEEE J. Solid State Circuits, 1996)

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. - Masayuki Mizuno; Yasushi Ooi; Naoya Hayashi; Junichi Goto; Masatoshi Hozumi; Koichiro Furuta; Atsufumi Shibayama; Yoetsu Nakazawa; Osamu Ohnishi; Shu-Yu Zhu; Yutaka Yokoyama; Yoichi Katayama; et al. (IEEE J. Solid State Circuits, 1997)

Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. - Koichiro Furuta; Taro Fujii; Masato Motomura; Kazutoshi Wakabayashi; Masakazu Yamashina (CICC, 2000)

A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. - Yuichiro Shibata; Masaki Uno; Hideharu Amano; Koichiro Furuta; Taro Fujii; Masato Motomura (FCCM, 2000)

Test Compression for Dynamically Reconfigurable Processors. - Hiroaki Inoue; Junya Yamada; Hideyuki Yoneda; Katsumi Togawa; Koichiro Furuta (FPL, 2010)

Test compression for dynamically reconfigurable processors. - Hiroaki Inoue; Junya Yamada; Hideyuki Yoneda; Katsumi Togawa; Masato Motomura; Koichiro Furuta (ACM Trans. Reconfigurable Technol. Syst., 2011)

C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join. - Eric Shun Fukuda; Hideyuki Kawashima; Hiroaki Inoue; Taro Fujii; Koichiro Furuta; Tetsuya Asai; Masato Motomura (ARC, 2013)

Optimizing time and space multiplexed computation in a dynamically reconfigurable processor. - Takao Toi; Noritsugu Nakamura; Taro Fujii; Toshiro Kitaoka; Katsumi Togawa; Koichiro Furuta; Toru Awashima (FPT, 2013)