Test Pattern Considerations for Fault Tolerant High Density DRAM. - Hiroshi Miyamoto; Koichiro Mashiko; Yoshikazu Morooka; Kazutami Arimoto; Michihiro Yamada; Takao Nakano (ITC, 1985)

A built-in Hamming code ECC circuit for DRAMs. - Kiyohiro Furutani; Kazutami Arimoto; Hiroshi Miyamoto; Toshifumi Kobayashi; Kenichi Yasuda; Koichiro Mashiko (IEEE J. Solid State Circuits, 1989)

A speed-enhanced DRAM array architecture with embedded ECC. - Kazutami Arimoto; Yoshio Matsuda; Kiyohiro Furutani; Masaki Tsukude; Tsukasa Ooishi; Koichiro Mashiko; Kuzuyasu Fujishima (IEEE J. Solid State Circuits, 1990)

A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates. - Toshiaki Hanibuchi; Masahiro Ueda; Keiichi Higashitani; Masahiro Hatanaka; Koichiro Mashiko; Akiharu Tada (IEEE J. Solid State Circuits, 1991)

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses. - Yutaka Arima; Koichiro Mashiko; Keisuke Okada; Tsuyoshi Yamada; Atsushi Maeda; Harufusa Kondoh; Shimpei Kayano (IEEE J. Solid State Circuits, 1991)

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing. - Yasunobu Nakase; Kakutaro Suda; Koichiro Mashiko; Tatsuhiko Ikeda; Shinpei Kayano (IEEE J. Solid State Circuits, 1991)

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture. - Yutaka Arima; Koichiro Mashiko; Keisuke Okada; Tsuyoshi Yamada; Atsushi Maeda; Hiromi Notani; Harufusa Kondoh; Shinpei Kayano (IEEE J. Solid State Circuits, 1991)

A voltage compensated series-gate bipolar circuit operating at sub-2 V. - Hisayasu Sato; Kimio Ueda; Nagisa Sasaki; Tatsuhiko Ikeda; Koichiro Mashiko (IEEE J. Solid State Circuits, 1994)

A BiCMOS wired-OR logic. - Yasunobu Nakase; Hiroaki Suzuki; Hiroshi Makino; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1995)

How to design low-power digital cellular phones. - Koichiro Mashiko (ISLPED, 1996)

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. - Hiroshi Makino; Yasunobu Nakase; Hiroaki Suzuki; Hiroyuki Morinaka; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1996)

A 286 MHz 64-b floating point multiplier with enhanced CG operation. - Hiroshi Makino; Hiroaki Suzuki; Hiroyuki Morinaka; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1996)

A 1.9-GHz single chip IF transceiver for digital cordless phones. - Hisayasu Sato; Kenichi Kashiwagi; Kazuhito Niwano; Tetsuya Iga; Tatsuhiko Ikeda; Koichiro Mashiko; Tadashi Sumi; Koji Tsuchihashi (IEEE J. Solid State Circuits, 1996)

Leading-zero anticipatory logic for high-speed floating point addition. - Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1996)

A fully compensated active pull-down ECL circuit with self-adjusting driving capability. - Kimio Ueda; Nagisa Sasaki; Hisayasu Sato; Koichiro Mashiko (IEEE J. Solid State Circuits, 1996)

A 64-bit carry look ahead adder using pass transistor BiCMOS gates. - Kiniio Ueda; Hiroaki Suzuki; Kakutaro Suda; Hirofumi Shinohara; Koichiro Mashiko (IEEE J. Solid State Circuits, 1996)

A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. - Hiroaki Suzuki; Hiroshi Makino; Koichiro Mashiko; Hisanori Hamano (ICCD, 1997)

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. - Vojin G. Oklobdzija; Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1997)

Authors Reply. - Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko (IEEE J. Solid State Circuits, 1997)

A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. - Toru Nakura; Kimio Ueda; Kazuo Kubo; Yoshio Matsuda; Koichiro Mashiko; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2000)

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. - Hao San; Akira Hayakawa; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Kazuyuki Kobayashi; Haruo Kobayashi 001; Tatsuji Matsuura; Kouichi Yahagi; Junya Kudoh; Hideo Nakane; Masao Hotta; et al. (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC. - Masafumi Uemori; Haruo Kobayashi 001; Tomonari Ichikawa; Atsushi Wada; Koichiro Mashiko; Toshiro Tsukada; Masao Hotta (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. - Hao San; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Akira Hayakawa; Haruo Kobayashi 001; Tatsuji Matsuura; Kouichi Yahagi; Junya Kudoh; Hideo Nakane; Masao Hotta; Toshiro Tsukada; et al. (IEICE Trans. Electron., 2007)

Evaluation of SRAM PUF Characteristics and Generation of Stable Bits for IoT Security. - Pyi Phyo Aung; Koichiro Mashiko; Nordinah Binti Ismail; Chia Yee Ooi (IRICT, 2019)