A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. - Fumiyasu Hirose; Koichiro Takayama; Nobuaki Kawato (ITC, 1988)

A high-speed test-generation method using a test generation circuit. - Fumiyasu Hirose; Koichiro Takayama; Nobuaki Kawato (Syst. Comput. Jpn., 1990)

An approach to verify a large scale system-on-a-chip using symbolic model checking. - Koichiro Takayama; Taizo Satoh; Tsuneo Nakata; Fumiyasu Hirose (ICCD, 1998)

Model Checking Based on Sequential ATPG. - Vamsi Boppana; Sreeranga P. Rajan; Koichiro Takayama; Masahiro Fujita (CAV, 1999)

An efficient filter-based approach for combinational verification. - Rajarshi Mukherjee; Jawahar Jain; Koichiro Takayama; Masahiro Fujita; Jacob A. Abraham; Donald S. Fussell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Automatic partitioning for efficient combinatorial verification. - Rajarshi Mukherjee; Jawahar Jain; Koichiro Takayama; Masahiro Fujita (ASP-DAC, 2000)

A New Functional Test Program Generation Methodology. - Farzan Fallah; Koichiro Takayama (ICCD, 2001)

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. - Subramanian Rajagopalan; Sreeranga P. Rajan; Sharad Malik; Sandro Rigo; Guido Araujo; Koichiro Takayama (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Effective safety property checking using simulation-based sequential ATPG. - Shuo Sheng; Koichiro Takayama; Michael S. Hsiao (DAC, 2002)

Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. - Rajarshi Mukherjee; Jawahar Jain; Koichiro Takayama; Jacob A. Abraham; Donald S. Fussell; Masahiro Fujita (Formal Methods Syst. Des., 2002)

High level hardware validation using hierarchical message sequence charts. - Praveen K. Murthy; Sreeranga P. Rajan; Koichiro Takayama (HLDVT, 2004)

Software Defect Prediction for LSI Designs. - Matthieu Parizy; Koichiro Takayama; Yuji Kanazawa (ICSME, 2014)