A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. - Daisuke Taki; Tatsuo Shiozawa; Kuniaki Ito; Youichiro Shiba; Kouji Horisaki; Hirotsugu Kajihara; Toshiyuki Yamagishi; Masahiro Sekiya; Akira Yamaga; Tetsuya Fujita; Hiroyuki Hara; Masanori Kuwahara; et al. (COOL Chips, 2011)

A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor. - Hideki Yamada; Toshiyuki Yamagishi; Tomoya Suzuki; Kuniaki Ito; Koji Horisaki; Tom Vander Aa; Toshio Fujisawa; Liesbet Van der Perre; Yasuo Unekawa (COOL Chips, 2011)

High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors. - Tomoya Suzuki; Hideki Yamada; Toshiyuki Yamagishi; Daisuke Takeda; Koji Horisaki; Tom Vander Aa; Toshio Fujisawa; Liesbet Van der Perre; Yasuo Unekawa (IEEE Micro, 2011)

An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation. - Toshiyuki Yamagishi; Tatsuo Shiozawa; Koji Horisaki; Hiroyuki Hara; Yasuo Unekawa (COOL Chips, 2012)

A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation. - Toshiyuki Yamagishi; Tatsuo Shiozawa; Koji Horisaki; Hiroyuki Hara; Yasuo Unekawa (IEICE Trans. Electron., 2013)