Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture. - Hiroaki Nakata; Koji Hosogi; Masakazu Ehama; Takafumi Yuasa; Toru Fujihira; Kenichi Iwata; Motoki Kimura; Fumitaka Izuhara; Seiji Mochizuki; Masaki Nobori (ASP-DAC, 2009)

A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS. - Kenichi Iwata; Seiji Mochizuki; Motoki Kimura; Tetsuya Shibayama; Fumitaka Izuhara; Hiroshi Ueda; Koji Hosogi; Hiroaki Nakata; Masakazu Ehama; Toru Kengaku; Takuichiro Nakazawa; Hiromi Watanabe (IEEE J. Solid State Circuits, 2009)