Optimizing the DRAM refresh count for merged DRAM/logic LSIs. - Taku Ohsawa; Koji Kai; Kazuaki J. Murakami (ISLPED, 1998)

Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. - Koji Inoue; Koji Kai; Kazuaki J. Murakami (HPCA, 1999)

Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. - Koji Inoue; Koji Kai; Kazuaki J. Murakami (Intelligent Memory Systems, 2000)

Prospective Silicon Applications and Technologies in 2025. - Koji Kai; Minoru Fujishima (IEICE Trans. Electron., 2011)