A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level. - Masaki Hashizume; Takeomi Tamesada; Koji Nii (ICCD, 1990)

LSSD Compatible and Concurrently Testable Ram. - Hideshi Maeno; Koji Nii; S. Sakayanagi; S. Kato (ITC, 1992)

A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates. - Koji Nii; Hideshi Maeno; Tokuya Osawa; Shuhei Iwade; Shinpei Kayano; Hiroshi Shibata (IEEE J. Solid State Circuits, 1995)

A low power SRAM using auto-backgate-controlled MT-CMOS. - Koji Nii; Hiroshi Makino; Yoshiki Tsujihashi; Chikayoshi Morishima; Yasushi Hayakawa; Hiroyuki Nunogami; Takahiko Arakawa; Hisanori Hamano (ISLPED, 1998)

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. - Koji Nii; Yasumasa Tsukamoto; Tomoaki Yoshizawa; Susumu Imaoka; Yoshinobu Yamagami; Toshikazu Suzuki; Akinori Shibayama; Hiroshi Makino; Shuhei Iwade (IEEE J. Solid State Circuits, 2004)

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. - Yasumasa Tsukamoto; Koji Nii; Susumu Imaoka; Yuji Oda; Shigeki Ohbayashi; Tomoaki Yoshizawa; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara (ICCAD, 2005)

A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. - Niichi Itoh; Yasumasa Tsukamoto; Takeshi Shibagaki; Koji Nii; Hidehiro Takata; Hiroshi Makino (ISCAS (1), 2005)

A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. - Hidehiro Fujiwara; Koji Nii; Junichi Miyakoshi; Yuichiro Murachi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2006)

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Kentaro Kawakami; Junichi Miyakoshi; Shinji Mikami; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. - Masanao Yamaoka; Noriaki Maeda; Yoshihiro Shinozaki; Yasuhisa Shimazaki; Koji Nii; Shigeru Shimada; Kazumasa Yanagisawa; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. - Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; et al. (ISSCC, 2007)

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. - Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (ISSCC, 2007)

A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Yasuhiro Morita; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISVLSI, 2007)

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Yusuke Iguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. - Yasuhiro Morita; Hidehiro Fujiwara; Hiroki Noguchi; Yusuke Iguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2007)

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. - Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; et al. (IEEE J. Solid State Circuits, 2007)

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. - Masako Fujii; Koji Nii; Hiroshi Makino; Shigeki Ohbayashi; Motoshige Igarashi; Takeshi Kawamura; Miho Yokota; Nobuhiro Tsuda; Tomoaki Yoshizawa; Toshikazu Tsutsui; Naohiko Takeshita; Naofumi Murata; et al. (IEICE Trans. Electron., 2008)

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Shunsuke Okumura; Yasuhiro Morita; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2008)

Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration. - Hirofumi Shinohara; Koji Nii; Hidetoshi Onodera (IEICE Trans. Electron., 2008)

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. - Satoshi Ishikura; Marefusa Kurumada; Toshio Terano; Yoshinobu Yamagami; Naoki Kotani; Katsuji Satomi; Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Toshiyuki Oashi; Hiroshi Makino; et al. (IEEE J. Solid State Circuits, 2008)

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (IEEE J. Solid State Circuits, 2008)

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. - Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; et al. (IEEE J. Solid State Circuits, 2008)

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. - Hidehiro Fujiwara; Koji Nii; Hiroki Noguchi; Junichi Miyakoshi; Yuichiro Murachi; Yasuhiro Morita; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. - Shunsuke Okumura; Yusuke Iguchi; Shusuke Yoshimoto; Hidehiro Fujiwara; Hiroki Noguchi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2009)

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. - Koji Nii; Yasumasa Tsukamoto; Makoto Yabuuchi; Yasuhiro Masuda; Susumu Imaoka; Keiichi Usui; Shigeki Ohbayashi; Hiroshi Makino; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2009)

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Yuuichi Hirano; Toshiaki Iwamatsu; Yuji Kihara (ISSCC, 2010)

Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. - Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Hirofumi Nakano; Kazuya Ishihara; Hiroyuki Kawai; Kazutami Arimoto (SoCC, 2010)

Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. - Yasumasa Tsukamoto; Takeshi Kida; T. Yamaki; Yuichiro Ishii; Koji Nii; Koji Tanaka; Shinji Tanaka; Yuji Kihara (CICC, 2011)

A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias. - Yukiko Umemoto; Koji Nii; Jiro Ishikawa; Kazuyoshi Okamoto; Kazutaka Mori; Kazumasa Yanagisawa (CICC, 2011)

A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. - Makoto Yabuuchi; Yasumasa Tsukamoto; Hidehiro Fujiwara; Shigeki Tawa; Koji Maekawa; Motoshige Igarashi; Koji Nii (ISLPED, 2011)

Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. - Hiroki Noguchi; Yusuke Iguchi; Hidehiro Fujiwara; Shunsuke Okumura; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. - Yuichiro Ishii; Hidehiro Fujiwara; Shinji Tanaka; Yasumasa Tsukamoto; Koji Nii; Yuji Kihara; Kazumasa Yanagisawa (IEEE J. Solid State Circuits, 2011)

A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. - Koji Nii; Yasumasa Tsukamoto; Yuichiro Ishii; Makoto Yabuuchi; Hidehiro Fujiwara; Kazuyoshi Okamoto (Asian Test Symposium, 2012)

A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology. - Kazuki Fukuoka; Ryo Mori; A. Kato; Motoshige Igarashi; Koji Shibutani; T. Yamaki; Shinji Tanaka; Koji Nii; Sadayuki Morita; Takao Koike; Noriaki Sakamoto (CICC, 2012)

Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. - Yasumasa Tsukamoto; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Changhwan Shin; Tsu-Jae King Liu (ISQED, 2012)

A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. - Yuichiro Ishii; Yasumasa Tsukamoto; Koji Nii; Hidehiro Fujiwara; Makoto Yabuuchi; Koji Tanaka; Shinji Tanaka; Yasuhisa Shimazaki (ISSCC, 2012)

A stable chip-ID generating physical uncloneable function using random address errors in SRAM. - Hidehiro Fujiwara; Makoto Yabuuchi; Yasumasa Tsukamoto; Hirofumi Nakano; Toru Owada; Hiroyuki Kawai; Koji Nii (SoCC, 2012)

Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation. - Takuya Sawada; Taku Toshikawa; Kumpei Yoshikawa; Hidehiro Takata; Koji Nii; Makoto Nagata (IEICE Trans. Electron., 2012)

Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. - Shusuke Yoshimoto; Takuro Amashita; Shunsuke Okumura; Koji Nii; Masahiko Yoshimoto; Hiroshi Kawaguchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Advanced memory topics. - Koji Nii; Toshiaki Kirihata (CICC, 2013)

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor. - Takao Nomura; Ryo Mori; Munehiro Ito; Koji Takayanagi; Toshihiko Ochiai; Kazuki Fukuoka; Kazuo Otsuga; Koji Nii; Sadayuki Morita; Tomoaki Hashimoto; Tsuyoshi Kida; Junichi Yamada; et al. (CICC, 2013)

A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure. - Makoto Yabuuchi; Hidehiro Fujiwara; Yasumasa Tsukamoto; Miki Tanaka; Shinji Tanaka; Koji Nii (CICC, 2013)

A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. - Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Yasumasa Tsukamoto; Yuichiro Ishii; Tetsuya Matsumura; Yoshio Matsuda (ISQED, 2013)

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor. - Masaki Fujigaya; Noriaki Sakamoto; Takao Koike; Takahiro Irita; Kohei Wakahara; Tsugio Matsuyama; Keiji Hasegawa; Toshiharu Saito; Akira Fukuda; Kaname Teranishi; Kazuki Fukuoka; Noriaki Maeda; et al. (ISSCC, 2013)

Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. - Shusuke Yoshimoto; Shunsuke Okumura; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. - Isamu Hayashi; Teruhiko Amano; Naoya Watanabe; Yuji Yano; Yasuto Kuroda; M. Shirata; Katsumi Dosaka; Koji Nii; Hideyuki Noda; Hiroyuki Kawai (IEEE J. Solid State Circuits, 2013)

A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. - Noriaki Maeda; Shigenobu Komatsu; Masao Morimoto; Koji Tanaka; Yasumasa Tsukamoto; Koji Nii; Yasuhisa Shimazaki (IEEE J. Solid State Circuits, 2013)

Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor. - Kazuki Fukuoka; Noriaki Maeda; Koji Nii; Masaki Fujigaya; Noriaki Sakamoto; Takao Koike; Takahiro Irita; Kohei Wakahara; Tsugio Matsuyama; Keiji Hasegawa; Toshiharu Saito; Akira Fukuda; et al. (IEEE Micro, 2013)

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues. - Yoshisato Yokoyama; Yuichiro Ishii; Koji Tanaka; Tatsuya Fukuda; Yoshiki Tsujihashi; Atsushi Miyanishi; Shinobu Asayama; Keiichi Maekawa; Kazutoshi Shiba; Koji Nii (A-SSCC, 2014)

The LSI implementation of a memory based field programmable device for MCU peripherals. - Tetsuya Matsumura; Naoya Okada; Yoshifumi Kawamura; Koji Nii; Kazutami Arimoto; Hiroshi Makino; Yoshio Matsuda (DDECS, 2014)

Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS. - Hidehiro Fujiwara; Makoto Yabuuchi; Koji Nii (ISQED, 2014)

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (ISQED, 2014)

40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU. - Yoshisato Yokoyama; Yuichiro Ishii; Hidemitsu Kojima; Atsushi Miyanishi; Yoshiki Tsujihashi; Shinobu Asayama; Kazutoshi Shiba; Koji Tanaka; Tatsuya Fukuda; Koji Nii; Kazumasa Yanagisawa (ISQED, 2014)

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores. - Mitsuhiko Igarashi; Toshifumi Uemura; Ryo Mori; Noriaki Maeda; Hiroshi Kishibe; Midori Nagayama; Masaaki Taniguchi; Kohei Wakahara; Toshiharu Saito; Masaki Fujigaya; Kazuki Fukuoka; Koji Nii; et al. (ISSCC, 2014)

13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM. - Koji Nii; Teruhiko Amano; Naoya Watanabe; Minoru Yamawaki; Kenji Yoshinaga; Mihoko Wada; Isamu Hayashi (ISSCC, 2014)

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. - Makoto Yabuuchi; Yasumasa Tsukamoto; Masao Morimoto; Miki Tanaka; Koji Nii (ISSCC, 2014)

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. - Shinji Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Toshiaki Sano; Koji Tanaka; Yasumasa Tsukamoto; Koji Nii; Hirotoshi Sato (VLSIC, 2014)

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. - Yohei Nakata; Yuta Kimi; Shunsuke Okumura; Jinwook Jung; Takuya Sawada; Taku Toshikawa; Makoto Nagata; Hirofumi Nakano; Makoto Yabuuchi; Hidehiro Fujiwara; Koji Nii; Hiroyuki Kawai; et al. (IEICE Trans. Electron., 2014)

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. - Yukiko Umemoto; Koji Nii; Jiro Ishikawa; Makoto Yabuuchi; Kazuyoshi Okamoto; Yasumasa Tsukamoto; Shinji Tanaka; Koji Tanaka; Tetsuya Matsumura; Kazutaka Mori; Kazumasa Yanagisawa (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU. - Yoshisato Yokoyama; Yuichiro Ishii; Toshihiro Inada; Koji Tanaka; Miki Tanaka; Yoshiki Tsujihashi; Koji Nii (A-SSCC, 2015)

A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2015)

An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology. - Mitsuhiko Igarashi; Kan Takeuchi; Takeshi Okagaki; Koji Shibutani; Hiroaki Matsushita; Koji Nii (ESSCIRC, 2015)

1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology. - Yasumasa Tsukamoto; Masao Morimoto; Makoto Yabuuchi; Miki Tanaka; Koji Nii (VLSIC, 2015)

Automotive low power technology for IoT society. - Tadaaki Yamauchi; Hiroyuki Kondo; Koji Nii (VLSIC, 2015)

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores. - Mitsuhiko Igarashi; Toshifumi Uemura; Ryo Mori; Hiroshi Kishibe; Midori Nagayama; Masaaki Taniguchi; Kohei Wakahara; Toshiharu Saito; Masaki Fujigaya; Kazuki Fukuoka; Koji Nii; Takeshi Kataoka; et al. (IEEE J. Solid State Circuits, 2015)

An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference. - Takuya Sawada; Kumpei Yoshikawa; Hidehiro Takata; Koji Nii; Makoto Nagata (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. - Yuichiro Ishii; Makoto Yabuuchi; Yohei Sawada; Masao Morimoto; Yasumasa Tsukamoto; Yuta Yoshida; Ken Shibata; Toshiaki Sano; Shinji Tanaka; Koji Nii (A-SSCC, 2016)

FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs. - Kan Takeuchi; Masaki Shimada; Takeshi Okagaki; Koji Shibutani; Koji Nii; Fumio Tsuchiya (ESSCIRC, 2016)

A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time. - Makoto Yabuuchi; Yohei Sawada; Toshiaki Sano; Yuichiro Ishii; Shinji Tanaka; Miki Tanaka; Koji Nii (VLSI Circuits, 2016)

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM. - Takao Nomura; Ryo Mori; Koji Takayanagi; Kazuki Fukuoka; Koji Nii (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. - Haruki Mori; Yohei Umeki; Shusuke Yoshimoto; Shintaro Izumi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2016)

A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode. - Yoshisato Yokoyama; Yuichiro Ishii; Haruyuki Okuda; Koji Nii (A-SSCC, 2017)

Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications. - Masanori Hayashikoshi; Hideyuki Noda; Hiroyuki Kawai; Koji Nii; Hiroyuki Kondo (COOL Chips, 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process. - Mitsuhiko Igarashi; Yuuki Uchida; Yoshio Takazawa; Yasumasa Tsukamoto; Koji Shibutani; Koji Nii (A-SSCC, 2018)

40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications. - Yoshisato Yokoyama; Tomohiro Miura; Yukari Ouchi; Daisuke Nakamura; Jiro Ishikawa; Shunya Nagata; Makoto Yabuuchi; Yuichiro Ishii; Koji Nii (A-SSCC, 2018)

Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET. - Mitsuhiko Igarashi; Yuuki Uchida; Yoshio Takazawa; Yasumasa Tsukamoto; Koji Shibutani; Koji Nii (IRPS, 2018)

12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM. - Makoto Yabuuchi; Masao Morimoto; Koji Nii; Shinji Tanaka (VLSI Circuits, 2018)

Wear-out stress monitor utilising temperature and voltage sensitive ring oscillators. - Kan Takeuchi; Masaki Shimada; Takeshi Okagaki; Koji Shibutani; Koji Nii; Fumio Tsuchiya (IET Circuits Devices Syst., 2018)

Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications. - Masanori Hayashikoshi; Hideyuki Noda; Hiroyuki Kawai; Yasumitsu Murai; Sugako Otani; Koji Nii; Yoshio Matsuda; Hiroyuki Kondo (IEEE Trans. Multi Scale Comput. Syst., 2018)

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. - Makoto Yabuuchi; Yasumasa Tsukamoto; Hidehiro Fujiwara; Miki Tanaka; Shinji Tanaka; Koji Nii (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. - Masanori Hayashikoshi; Hiroaki Tanizaki; Yasumitsu Murai; Takaharu Tsuji; Kiyoshi Kawabata; Koji Nii; Hideyuki Noda; Hiroyuki Kondo; Yoshio Matsuda; Hideto Hidaka (IEICE Trans. Electron., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Cost-Effective Embedded Nonvolatile Memory with Scalable LEE Flash®-G2 SONOS for Secure IoT and Computing-in-Memory (CiM) Applications. - Koji Nii; Yasuhiro Taniguchi; Kosuke Okuyama (VLSI-DAT, 2020)

Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs. - Yoshisato Yokoyama; Yuichiro Ishii; Koji Nii; Kazutoshi Kobayashi (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. - Yumito Aoyagi; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. - Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Jhon-Jhy Liaw; Shien-Yang Michael Wu; Quincy Li; Hidehiro Fujiwara; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing. - Yoshisato Yokoyama; Koji Nii; Yuichiro Ishii; Shinji Tanaka; Kazutoshi Kobayashi (IEEE J. Solid State Circuits, 2023)

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (ISSCC, 2024)

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction. - Tomotaka Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Yumito Aoyagi; Masaya Hamada; Kazuto Mizutani; Koji Nii; Hidehiro Fujiwara; Isabel Wang; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2024)

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. - Yumito Aoyagi; Koji Nii; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2024)

A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications. - Yoshiaki Osada; Takaaki Nakazato; Yumito Aoyagi; Koji Nii; Jhon-Jhy Liaw; Shien-Yang Wu; Quincy Li; Hidehiro Fujiwara; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)