Performance analysis of a time diversity ARQ in land mobile radio. - Fumiyuki Adachi; S. Ito; Koji Ohno (IEEE Trans. Commun., 1989)

Performance of coherent detection and RAKE for DS-CDMA uplink channels. - Akihiro Higashi; Tsutomu Taguchi; Koji Ohno (PIMRC, 1995)

Field Experiment Results of User Throughput Performance in WCDMA HSDPA. - Yousuke Iizuka; Takeshi Nakamori; Hiroyuki Ishii; Shinya Tanaka; Shinsuke Ogawa; Koji Ohno (PIMRC, 2005)

Hierarchical power distribution and power management scheme for a single chip mobile processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (DAC, 2006)

SH-MobileG1: A single-chip application and dual-mode baseband processor. - Masayuki Ito; Takahiro Irita; Eiji Yamamoto; Kunihiko Nishiyama; Takao Koike; Yoshihiko Tsuchihashi; Hiroyuki Asano; Hiroshi Yagi; Saneaki Tamaki; Ken Tatezawa; Toshihiro Hattori; Shinichi Yoshioka; et al. (Hot Chips Symposium, 2006)

A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (ISSCC, 2006)

A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS. - Masayuki Ito; Toshihiro Hattori; Takahiro Irita; Ken Tatezawa; Fumihito Tanaka; Kenji Hirose; Shinichi Yoshioka; Koji Ohno; Reiko Tsuchihashi; Minoru Sakata; Masayuki Yamamoto; Yuji Aral (ISSCC, 2007)

A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU. - Masao Naruse; Tatsuya Kamei; Toshihiro Hattori; Takahiro Irita; Kenichi Nitta; Takao Koike; Shinichi Yoshioka; Koji Ohno; Masahito Saigusa; Minoru Sakata; Yukio Kodama; Yuji Arai; et al. (ISSCC, 2008)

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU. - Masayuki Ito; Kenichi Nitta; Koji Ohno; Masahito Saigusa; Masaki Nishida; Shinichi Yoshioka; Takahiro Irita; Takao Koike; Tatsuya Kamei; Teruyoshi Komuro; Toshihiro Hattori; Yasuhiro Arai; et al. (IEEE J. Solid State Circuits, 2009)