A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis. - Rie Soejima; Koji Okina; Keisuke Dohi; Yuichiro Shibata; Kiyoshi Oguri (SIGARCH Comput. Archit. News, 2014)

Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space Exploration. - Keisuke Dohi; Koji Okina; Rie Soejima; Yuichiro Shibata; Kiyoshi Oguri (IEICE Trans. Inf. Syst., 2015)

Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization. - Koji Okina; Rie Soejima; Kota Fukumoto; Yuichiro Shibata; Kiyoshi Oguri (SIGARCH Comput. Archit. News, 2015)