An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. - Shigeyoshi Watanabe; Yukihito Oowaki; Yasuo Itoh; Koji Sakui; Kenji Numata; Tsuneaki Fuse; Takayuki Kobayashi; Kenji Tsuchida; Masahiko Chiba; Takahiko Hara; Masako Ohta; Fumio Horiguchi; et al. (IEEE J. Solid State Circuits, 1989)

BiCMOS circuit technology for high-speed DRAMs. - Shigeyoshi Watanabe; Koji Sakui; Tsuneaki Fuse; Takahiko Hara; Seiichi Aritome; Katsuhiko Hieda (IEEE J. Solid State Circuits, 1993)

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. - Tomoharu Tanaka; Yoshiyuki Tanaka; Hiroshi Nakamura; Koji Sakui; Hideko Oodaira; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka; Hisashi Hara (IEEE J. Solid State Circuits, 1994)

A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed. - Jin-Ki Kim; Koji Sakui; Sung-Soo Lee; Yasuo Itoh; Suk-Chon Kwon; Kazuhisa Kanazawa; Ki-Jun Lee; Hiroshi Nakamura; Kang-Young Kim; Toshihiko Himeno; Jang-Rae Kim; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 1997)

A CMOS bandgap reference circuit with sub-1-V operation. - Hironori Banba; Hitoshi Shiga; Akira Umezawa; Takeshi Miyaba; Toru Tanzawa; Shigeru Atsumi; Koji Sakui (IEEE J. Solid State Circuits, 1999)

A 130-mm/2, 256-Mbit NAND flash with shallow trench isolation technology. - Kenichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Toshihiko Himeno; Ken Takeuchi; Tamio Ikehashi; Kazushige Kanda; Koji Hosono; Riichiro Shirota; Seiichi Aritome; Kazuhiro Shimizu; Kazuo Hatakeyama; et al. (IEEE J. Solid State Circuits, 1999)

A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories. - Ken Takeuchi; Shinji Satoh; Tomoharu Tanaka; Ken-ichi Imamiya; Koji Sakui (IEEE J. Solid State Circuits, 1999)

A source-line programming scheme for low-voltage operation NAND flash memories. - Ken Takeuchi; Shinji Satoh; Ken-ichi Imamiya; Koji Sakui (IEEE J. Solid State Circuits, 2000)

A compact and low power logic design for multi-pillar vertical MOSFETs. - Koji Sakui; Tetsuo Endoh (ISCAS, 2010)

Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure. - Tetsuo Endoh; Koji Sakui; Yukio Yasuda (IEICE Trans. Electron., 2010)

Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET. - Tetsuo Endoh; Koji Sakui; Yukio Yasuda (IEICE Trans. Electron., 2010)

High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology. - Koji Sakui; Takayuki Ohba (3DIC, 2019)

Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform. - Koji Sakui; Takayuki Ohba (CICC, 2019)

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar. - Yisuo Li; Ken'ichi Kanazawa; Tetsuo Izawa; Koji Sakui; Georg Strof; Oskar Baumgartner; Gerhard Rzepa; Markus Karner; Zlatan Stanojevic; Nozomu Harada; Fujio Masuoka (IMW, 2021)

Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT). - Koji Sakui; Nozomu Harada (IMW, 2021)

Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs. - Zhwen Chen; Young-Suk Kim; Tadashi Fukuda; Koji Sakui; Takayuki Ohba; Tatsuji Kobayashi; Takashi Obara (IRPS, 2021)

Dynamic Flash Memory with Fast Block Refresh. - Koji Sakui; Masakazu Kakumu; Nozomu Harada (NVMTS, 2022)

Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy. - Norio Chujo; Koji Sakui; Shinji Sugatani; Hiroyuki Ryoson; Tomoji Nakamura; Takayuki Ohba (VLSI Technology and Circuits, 2023)

Dynamic Flash Memory Operation Experimentally Validated with 65nm SOI Technology. - Koji Sakui; Daniele Garbin; Yoshihisa Iwata; Gautam Gaddemane; Yisuo Li; Yiqun Wan; Ken'ichi Kanazawa; Eyup Can Demir; Iwao Kunishima; Andrea Fantini; Masakazu Kakumu; Christophe Lorant; et al. (IMW, 2025)

Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WOW and COW. - Norio Chujo; Hiroyuki Ryoson; Koji Sakui; Shinji Sugatani; Masao Taguchi; Takayuki Ohba (IEEE J. Emerg. Sel. Topics Circuits Syst., 2025)

A Through Silicon Via (TSV) Architecture of the Bumpless Build Cube (BBCube) for Stacked Memory Devices. - Shinji Sugatani; Hiroyuki Ryoson; Norio Chujo; Masao Taguchi; Koji Sakui; Takayuki Ohba (IEEE J. Emerg. Sel. Topics Circuits Syst., 2025)