Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor. - Takao Nomura; Ryo Mori; Munehiro Ito; Koji Takayanagi; Toshihiko Ochiai; Kazuki Fukuoka; Kazuo Otsuga; Koji Nii; Sadayuki Morita; Tomoaki Hashimoto; Tsuyoshi Kida; Junichi Yamada; et al. (CICC, 2013)

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM. - Takao Nomura; Ryo Mori; Koji Takayanagi; Kazuki Fukuoka; Koji Nii (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)