Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS. - David Halupka; Safeen Huda; William Song; Ali Sheikholeslami; Koji Tsunoda; Chikako Yoshida; Masaki Aoki (ISSCC, 2010)

STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A negative-resistance sense amplifier for low-voltage operating STT-MRAM. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (ASP-DAC, 2015)

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. - Yohei Umeki; Koji Yanagida; Shusuke Yoshimoto; Shintaro Izumi; Masahiko Yoshimoto; Hiroshi Kawaguchi 001; Koji Tsunoda; Toshihiro Sugii (IPSJ Trans. Syst. LSI Des. Methodol., 2016)