25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. - Tomonori Tanaka; Kosuke Furuichi; Hiromu Uemura; Ryosuke Noguchi; Natsuyuki Koda; Koki Arauchi; Daichi Omoto; Hiromi Inaba; Keiji Kishine; Shinsuke Nakano; Masafumi Nogawa; Hideyuki Nosaka (ISCAS, 2017)

Compact implementation IIR filter in FPGA for noise reduction of sensor signal. - Koki Arauchi; Shohei Maki; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2017)