A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. - Koki Igawa; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (SoCC, 2015)

A delay variation and floorplan aware high-level synthesis algorithm with body biasing. - Koki Igawa; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ISQED, 2016)

Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms. - Koki Igawa; Masao Yanagisawa; Nozomu Togawa (IEICE Electron. Express, 2016)

A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design. - Koki Igawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation. - Koki Igawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)