A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck. - Toshiki Kanamoto; Masami Fukushima; Koichi Kitagishi; Seijin Nakayama; Hideki Ishihara; Koki Kasai; Atsushi Kurokawa; Masashi Imai (MWSCAS, 2019)

A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis. - Toshiki Kanamoto; Koki Kasai; Kan Hatakeyama; Atsushi Kurokawa; Tomoyuki Nagase; Masashi Imai (IEICE Electron. Express, 2020)

Running trajectory optimization to mitigate delay propagation in highly frequent train service based on continuous train position acquisition. - Keisuke Sakai; Wataru Ohnishi; Takafumi Koseki; Kazuhiro Tanaka; Shunji Morita; Katsutoshi Tokuhara; Koki Kasai (ISIE, 2021)