Implications of Memory Performance for Highly Efficient Supercomputing of Scientific Applications. - Akihiro Musa; Hiroyuki Takizawa; Koki Okabe; Takashi Soga; Hiroaki Kobayashi (ISPA, 2006)

An on-chip cache design for vector processors. - Akihiro Musa; Yoshiei Sato; Ryusuke Egawa; Hiroyuki Takizawa; Koki Okabe; Hiroaki Kobayashi (MEDEA@PACT, 2007)

First Experiences with NEC SX-9. - Hiroaki Kobayashi; Ryusuke Egawa; Hiroyuki Takizawa; Koki Okabe; Akihiko Musa; Takashi Soga; Yoichi Shimomura (High Performance Computing on Vector Systems, 2008)

Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture. - Akihiro Musa; Yoshiei Sato; Takashi Soga; Ryusuke Egawa; Hiroyuki Takizawa; Koki Okabe; Hiroaki Kobayashi (ISPA, 2008)

A shared cache for a chip multi vector processor. - Akihiro Musa; Yoshiei Sato; Takashi Soga; Koki Okabe; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (MEDEA@PACT, 2008)

Performance tuning and analysis of future vector processors based on the roofline model. - Yoshiei Sato; Ryu-ichi Nagaoka; Akihiro Musa; Ryusuke Egawa; Hiroyuki Takizawa; Koki Okabe; Hiroaki Kobayashi (MEDEA@PACT, 2009)

Performance evaluation of NEC SX-9 using real science and engineering applications. - Takashi Soga; Akihiro Musa; Youichi Shimomura; Ryusuke Egawa; Ken'ichi Itakura; Hiroyuki Takizawa; Koki Okabe; Hiroaki Kobayashi (SC, 2009)