Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. - Martin Kumm; Konrad Möller; Peter Zipf (ISCAS, 2013)

Reconfigurable FIR filter using distributed arithmetic on FPGAs. - Martin Kumm; Konrad Möller; Peter Zipf (ISCAS, 2013)

Dynamically reconfigurable FIR filter architectures with fast reconfiguration. - Martin Kumm; Konrad Möller; Peter Zipf (ReCoSoC, 2013)

FIR filter optimization for video processing on FPGAs. - Martin Kumm; Diana Fanghänel; Konrad Möller; Peter Zipf; Uwe Meyer-Baese (EURASIP J. Adv. Signal Process., 2013)

Pipelined reconfigurable multiplication with constants on FPGAs. - Konrad Möller; Martin Kumm; Marco Kleinlein; Peter Zipf (FPL, 2014)

Dynamically Reconfigurable Constant Multiplication on FPGAs. - Konrad Möller; Martin Kumm; Björn Barschtipan; Peter Zipf (MBMV, 2014)

Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. - Konrad Möller; Martin Kumm; Charles-Frederic Müller; Peter Zipf (CoRR, 2015)

Model-based hardware design based on compatible sets of isomorphic subgraphs. - Patrick Sittel; Konrad Möller; Martin Kumm; Peter Zipf; Bogdan Pasca 001; Mark Jervis (FPT, 2017)

High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. - Patrick Sittel; Martin Kumm; Konrad Möller; Martin Hardieck; Peter Zipf (MBMV, 2017)

Reconfigurable Constant Multiplication for FPGAs. - Konrad Möller; Martin Kumm; Marco Kleinlein; Peter Zipf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Run-time Reconfigurable Constant Multiplication on Field Programmable Gate Arrays. - Konrad Möller (2017)

ILP-Based Modulo Scheduling and Binding for Register Minimization. - Patrick Sittel; Martin Kumm; Julian Oppermann; Konrad Möller; Peter Zipf; Andreas Koch 001 (FPL, 2018)

Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. - Konrad Möller; Martin Kumm; Mario Garrido; Peter Zipf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. - Martin Hardieck; Martin Kumm; Konrad Möller; Peter Zipf (FPGA, 2019)

World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s. - Mario Garrido; Konrad Möller; Martin Kumm (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)