Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. - Konstantin Moiseev; Shmuel Wimer; Avinoam Kolodny (ISCAS, 2006)

Optimal bus sizing in migration of processor design. - Shmuel Wimer; Shay Michaely; Konstantin Moiseev; Avinoam Kolodny (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

On optimal ordering of signals in parallel wire bundles. - Konstantin Moiseev; Shmuel Wimer; Avinoam Kolodny (Integr., 2008)

Timing-aware power-optimal ordering of signals. - Konstantin Moiseev; Avinoam Kolodny; Shmuel Wimer (ACM Trans. Design Autom. Electr. Syst., 2008)

Power-delay optimization in VLSI microprocessors by wire spacing. - Konstantin Moiseev; Avinoam Kolodny; Shmuel Wimer (ACM Trans. Design Autom. Electr. Syst., 2009)

Interconnect power and delay optimization by dynamic programming in gridded design rules. - Konstantin Moiseev; Avinoam Kolodny; Shmuel Wimer (ISPD, 2010)

Interconnect Bundle Sizing Under Discrete Design Rules. - Konstantin Moiseev; Avinoam Kolodny; Shmuel Wimer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

The complexity of VLSI power-delay optimization by interconnect resizing. - Konstantin Moiseev; Avinoam Kolodny; Shmuel Wimer (J. Comb. Optim., 2012)

Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. - Konstantin Moiseev; Shmuel Wimer; Avinoam Kolodny (Integr., 2015)