Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. - Dimitrios Soudris; Nikolaos D. Zervas; Antonios Argyriou; Minas Dasygenis; Konstantinos Tatas; Constantinos E. Goutis; Adonios Thanailakis (PATMOS, 2000)

Data and instruction memory exploration of embedded systems for multimedia applications. - Minas Dasygenis; Nikolas Kroupis; Antonios Argyriou; Konstantinos Tatas; Dimitrios Soudris; Nikolaos D. Zervas (ICASSP, 2001)

Power, performance and area exploration of block matching algorithms mapped on programmable processors. - Nikolas Kroupis; Minas Dasygenis; Antonios Argyriou; Konstantinos Tatas; Dimitrios Soudris; Antonios Thanailakis; Nikolaos D. Zervas; Constantinos E. Goutis (ICIP (3), 2001)

Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1. - Konstantinos Tatas; Antonios Argyriou; Minas Dasygenis; Dimitrios Soudris; Nikolaos D. Zervas (ISQED, 2001)

Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. - George Koutroumpezis; Konstantinos Tatas; Dimitrios Soudris; Spyros Blionas; Kostas Masselos; Adonios Thanailakis (FPL, 2002)

A full adder based methodology for scaling operation in residue number system. - Dimitrios Soudris; Minas Dasygenis; K. Mitroglou; Konstantinos Tatas; Adonios Thanailakis (ICECS, 2002)

A novel division algorithm for parallel and sequential processing. - Konstantinos Tatas; D. J. Soudris; D. Siomos; Minas Dasygenis; Adonios Thanailakis (ICECS, 2002)

Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. - Konstantinos Tatas; Kostas Siozios; Dimitrios Soudris; Adonios Thanailakis (FPL, 2003)

A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. - Dimitrios Soudris; K. Sgouropoulos; Konstantinos Tatas; Vasilis F. Pavlidis; Adonios Thanailakis (ISCAS (5), 2003)

Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. - Konstantinos Tatas; Kostas Siozios; Dimitrios Soudris; Adonios Thanailakis; Kostas Masselos; Konstantinos Potamianos; Spyros Blionas (PATMOS, 2003)

FPGA Architecture Design and Toolset for Logic Implementation. - Konstantinos Tatas; Kostas Siozios; Nikolaos Vassiliadis; D. J. Soudris; Spiridon Nikolaidis 001; Stilianos Siskos; Adonios Thanailakis (PATMOS, 2003)

Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. - Konstantinos Tatas; Minas Dasygenis; Nikolas Kroupis; Antonios Argyriou; Dimitrios Soudris; Antonios Thanailakis (Real Time Imaging, 2003)

A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. - Kostas Siozios; George Koutroumpezis; Konstantinos Tatas; Dimitrios Soudris; Adonios Thanailakis (FPL, 2004)

An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. - Vasilios Kalenteridis; Haroula Pournara; Kostas Siozios; Konstantinos Tatas; George Koutroumpezis; Ilias Pappas 001; Spiridon Nikolaidis 001; Stilianos Siskos; D. J. Soudris; Adonios Thanailakis (IPDPS, 2004)

A reusable IP FFT core for DSP applications. - Evaggelia Theochari; Konstantinos Tatas; Dimitrios Soudris; Kostas Masselos; Konstantinos Potamianos; Spyros Blionas; Antonios Thanailakis (ISCAS (3), 2004)

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. - Dimitrios Soudris; Spiridon Nikolaidis 001; Stilianos Siskos; Konstantinos Tatas; Kostas Siozios; George Koutroumpezis; Nikolaos Vassiliadis; Vasilios Kalenteridis; Haroula Pournara; Ilias Pappas 001; Adonios Thanailakis (ASP-DAC, 2005)

An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. - Kostas Siozios; Konstantinos Tatas; George Koutroumpezis; D. J. Soudris; Adonios Thanailakis (FPL, 2005)

DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. - Kostas Siozios; George Koutroumpezis; Konstantinos Tatas; Dimitrios Soudris; Adonios Thanailakis (IPDPS, 2005)

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. - Kostas Siozios; George Koutroumpezis; Konstantinos Tatas; Nikolaos Vassiliadis; Vasilios Kalenteridis; Haroula Pournara; Ilias Pappas 001; Dimitrios Soudris; Antonios Thanailakis; Spiridon Nikolaidis 001; Stilianos Siskos (IEICE Trans. Inf. Syst., 2005)

A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. - Konstantinos Tatas; Dimitrios Soudris; D. Siomos; Adonios Thanailakis (J. Circuits Syst. Comput., 2005)

Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms. - Konstantinos Tatas; Dimitrios Soudris; Adonios Thanailakis (J. Embed. Comput., 2005)

A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. - Vasilios Kalenteridis; Haroula Pournara; Kostas Siozios; Konstantinos Tatas; Nikolaos Vassiliadis; Ilias Pappas 001; George Koutroumpezis; Spiridon Nikolaidis 001; Stilianos Siskos; D. J. Soudris (Microprocess. Microsystems, 2005)

A novel methodology for designing high-performance and low-energy FPGA routing architecture. - Kostas Siozios; Konstantinos Tatas; Dimitrios Soudris; Antonios Thanailakis (FPGA, 2006)

Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. - Kostas Siozios; Konstantinos Tatas; Dimitrios Soudris; Adonios Thanailakis (IPDPS, 2006)

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. - Nikolas Kroupis; Nikolaos D. Zervas; Minas Dasygenis; Konstantinos Tatas; Antonios Argyriou; Dimitrios Soudris; Antonios Thanailakis (J. VLSI Signal Process., 2006)

Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. - Konstantinos Tatas; George Koutroumpezis; Dimitrios Soudris; Adonios Thanailakis (Integr., 2007)

Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs. - Konstantinos Tatas; Costas Kyriacou; Paraskevas Evripidou; Pedro Trancoso; Stephan Wong (Parallel Process. Lett., 2008)

A novel fuzzy logic based bufferless routing algorithm for low-power NoCs. - Konstantinos Tatas; Chrysostomos Chrysostomou (BCFIC, 2012)

A Dynamic Fuzzy Logic Based Routing Scheme for Bufferless NoCs. - Chrysostomos Chrysostomou; Konstantinos Tatas; A. R. Runcan (CSE, 2012)

A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC. - Konstantinos Tatas; Kostas Siozios; Alexandros Bartzas; Costas Kyriacou; Dimitrios Soudris (Int. J. Adapt. Resilient Auton. Syst., 2013)

Low-cost fault-tolerant routing for regular topology NoCs. - Konstantinos Tatas; S. Sawa; Costas Kyriacou (ICECS, 2014)

Adaptive Networks-on-Chip Routing with Fuzzy Logic Control. - Konstantinos Tatas; Chrysostomos Chrysostomou (DSD, 2016)

3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D Networks-on-Chip. - Konstantinos Tatas; Savvas Sava; Costas Kyriacou (PATMOS, 2017)

Hardware implementation of dynamic fuzzy logic based routing in Network-on-Chip. - Konstantinos Tatas; Chrysostomos Chrysostomou (Microprocess. Microsystems, 2017)

Towards Dynamic Multi-task Schedulling of OpenCL Programs on Emerging CPU-GPU-FPGA Heterogeneous Platforms: A Fuzzy Logic Approach. - Ahmad Al-Zoubi; Konstantinos Tatas; Costas Kyriacou (CloudCom, 2018)

Design space exploration of the KNN imputation on FPGA. - Ahmad Al-Zoubi; Konstantinos Tatas; Costas Kyriacou (MOCAST, 2018)

High-performance 3D NoC bufferless router with approximate priority comparison. - Konstantinos Tatas (MOCAST, 2018)

Fuzzy classification of OpenCL programs targeting heterogeneous systems. - Ahmad Al-Zoubi; Konstantinos Tatas; Costas Kyriacou (J. Intell. Fuzzy Syst., 2020)

Towards an Analytical Model of Latency in Deflection Routing: A Stochastic Process Approach for Bufferless NoCs. - Konstantinos Tatas (MOCAST, 2021)

iPONICS: IoT Monitoring and Control for Hydroponics. - Konstantinos Tatas; Ahmad Al-Zoubi; A. Antoniou 001; D. Zolotareva (MOCAST, 2021)

A Low-Cost Real-Time Cyber Physical System for Overcoming Excess Braking Issues In Race Cars. - V. Samaras; Konstantinos Tatas; Antonios Lontos (MOCAST, 2023)

PDU: A Pill Dispenser Unit for an IoT System for Monitoring and Controlling the Pharmaceutical Treatment for Patients With Psychological Mental Conditions. - Marios Savvides; Costas Kyriacou; Victoras Kassianides; Christos Markides; Konstantinos Tatas (IC3INA, 2024)

WIDE: Worksheet Integrated Development Environment for Arduino-Based Embedded System Design. - N. Ioannou; Konstantinos Tatas; A. Constantinides; Costas Kyriacou (MOCAST, 2024)

Artemis: IoT-Based Shooting Range Management System. - Konstantinos Tatas; Christos Markides; Victoras Kassianides; Nicos Hadjisofokli (MOCAST, 2024)