A broadband RF 65 nm CMOS front-end for cable TV reception. - Marco Pifferi; Fabio Ducati; Hans Brekelmans; Lorenzo Tripodi; Kostas Doris; Mattia Borgarino (Microelectron. J., 2008)

An 11b pipeline ADC with dual sampling technique for converting multi-carrier signals. - Yu Lin 003; Kostas Doris; Hans Hegt; Arthur H. M. van Roermund (ISCAS, 2011)

A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS. - Kostas Doris; Erwin Janssen; Claudio Nani; Athon Zanikopoulos; Gerard van der Weide (IEEE J. Solid State Circuits, 2011)

A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < - 83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping. - Yongjian Tang; Joost Briaire; Kostas Doris; Robert H. M. van Veldhoven; Pieter C. W. van Beek; Hans Hegt; Arthur H. M. van Roermund (IEEE J. Solid State Circuits, 2011)

A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS. - Yu Lin 003; Kostas Doris; Hans Hegt; Arthur H. M. van Roermund (ISCAS, 2012)

An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals. - Yu Lin 003; Kostas Doris; Hans Hegt; Arthur H. M. van Roermund (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals. - Yu Lin 003; Kostas Doris; Erwin Janssen; Athon Zanikopoulos; Alessandro Murroni; Gerard van der Weide; Hans Hegt; Arthur H. M. van Roermund (ESSCIRC, 2013)

An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS. - Erwin Janssen; Kostas Doris; Athon Zanikopoulos; Alessandro Murroni; Gerard van der Weide; Yu Lin 003; Ludo Alvado; Frederic Darthenay; Yannick Fregeais (ISSCC, 2013)

15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS. - Martin Kramer; Erwin Janssen; Kostas Doris; Boris Murmann (ISSCC, 2015)

A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS. - Martin Kramer; Erwin Janssen; Kostas Doris; Boris Murmann (IEEE J. Solid State Circuits, 2015)

F2: Data-converter calibration and dynamic-matching techniques. - Kostas Doris; Alyosha C. Molnar; Xicheng Jiang; Seung-Tak Ryu (ISSCC, 2016)

Session 27 overview: Hybrid and nyquist data converters. - Stéphane Le Tual; Kostas Doris (ISSCC, 2016)

F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX. - Kostas Doris; David Robertson 002; Seung-Tak Ryu; Seng-Pan U (ISSCC, 2017)

A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting. - Martin Kramer; Erwin Janssen; Kostas Doris; Boris Murmann (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

EE4: Figures-of-merit on trial. - Kostas Doris; Stefano Stanzione; Paul Ferguson (ISSCC, 2018)

Session 22 overview: Gigahertz data converters: Data converter subcommittee. - Kostas Doris; Jan Westra; Un-Ku Moon (ISSCC, 2018)

EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!). - Phillip J. Restle; Kostas Doris; Vivek De; Paul Ferguson (ISSCC, 2018)

A novel analysis of the beam squinting in wideband phased array digital I/Q transmitters. - Veselin Manev; Marios Neofytou; Georgi I. Radulov; Kostas Doris (ECCTD, 2020)

Time Interleaved ADC Mismatch Error Correction Technique in I/Q Digital Beamforming Receivers. - Pavlos Athanasiadis; Marios Neofytou; Marcello Ganzerli; Georgi I. Radulov; Kostas Doris (ISCAS, 2021)

A Novel 2-Dimensional Correction Method for mm-Wave Cartesian I/Q Modulators. - Marios Neofytou; Pavlos Athanasiadis; Marcello Ganzerli; Maarten Lont; Georgi I. Radulov; Kostas Doris (ISCAS, 2021)

32.6 A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC Radar-Waveform Synthesizer. - Marios Neofytou; Kostas Doris; Marcello Ganzerli; Maarten Lont; Georgi I. Radulov (ISSCC, 2024)