A pure-CMOS nonvolatile multi-context configuration memory for dynamically reconfigurable FPGAs. - Kosuke Tatsumura; Masato Oda; Shinichi Yasuda (FPT, 2014)

High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs. - Kosuke Tatsumura; Sadegh Yazdanshenas; Vaughn Betz (FPT, 2016)

Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration. - Sadegh Yazdanshenas; Kosuke Tatsumura; Vaughn Betz (FPGA, 2017)

Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs. - Kosuke Tatsumura; Sadegh Yazdanshenas; Vaughn Betz (ACM Trans. Reconfigurable Technol. Syst., 2018)

FPGA-Based Simulated Bifurcation Machine. - Kosuke Tatsumura; Alexander Dixon; Hayato Goto (FPL, 2019)

A Currency Arbitrage Machine Based on the Simulated Bifurcation Algorithm for Ultrafast Detection of Optimal Opportunity. - Kosuke Tatsumura; Ryo Hidaka; Masaya Yamasaki; Yoshisato Sakai; Hayato Goto (ISCAS, 2020)

Live Demonstration: Capturing Short-Lived Currency Arbitrage Opportunities with a Simulated Bifurcation Algorithm-Based Trading System. - Masaya Yamasaki; Ryo Hidaka; Yoshisato Sakai; Jun Yamaguchi; Yasuhito Nakamura; Hayato Goto; Kosuke Tatsumura (ISCAS, 2020)

Large-scale combinatorial optimization in real-time systems by FPGA-based accelerators for simulated bifurcation. - Kosuke Tatsumura (HEART, 2021)

Correlation-Diversified Portfolio Construction by Finding Maximum Independent Set in Large-Scale Market Graph. - Ryo Hidaka; Yohei Hamakawa; Jun Nakayama; Kosuke Tatsumura (IEEE Access, 2023)

Pairs-Trading System Using Quantum-Inspired Combinatorial Optimization Accelerator for Optimal Path Search in Market Graphs. - Kosuke Tatsumura; Ryo Hidaka; Jun Nakayama; Tomoya Kashimata; Masaya Yamasaki (IEEE Access, 2023)

Real-Time Trading System Based on Selections of Potentially Profitable, Uncorrelated, and Balanced Stocks by NP-Hard Combinatorial Optimization. - Kosuke Tatsumura; Ryo Hidaka; Jun Nakayama; Tomoya Kashimata; Masaya Yamasaki (IEEE Access, 2023)

Roadmap for Unconventional Computing with Nanotechnology. - Giovanni Finocchio; Supriyo Bandyopadhyay; Peng Lin; Gang Pan 001; J. Joshua Yang; Riccardo Tomasello; Christos Panagopoulos; Mario Carpentieri; Vito Puliafito; Johan Åkerman; Hiroki Takesue; Amit Ranjan Trivedi; et al. (CoRR, 2023)

Ultra-High-Speed Optimization for 5G Wireless Resource Allocation by Simulated Bifurcation Machine. - Haruka Obata; Toshihisa Nabetani; Hayato Goto; Kosuke Tatsumura (WCNC, 2024)

Efficient and Scalable Architecture for Multiple-Chip Implementation of Simulated Bifurcation Machines. - Tomoya Kashimata; Masaya Yamasaki; Ryo Hidaka; Kosuke Tatsumura (IEEE Access, 2024)

Collaborative filtering based on nonnegative/binary matrix factorization. - Yukino Terui; Yuka Inoue; Yohei Hamakawa; Kosuke Tatsumura; Kazue Kudo (CoRR, 2024)

Enhancing In-vehicle Multiple Object Tracking Systems with Embeddable Ising Machines. - Kosuke Tatsumura; Yohei Hamakawa; Masaya Yamasaki; Koji Oya; Hiroshi Fujimoto (CoRR, 2024)

Machine Learning-assisted High-speed Combinatorial Optimization with Ising Machines for Dynamically Changing Problems. - Yohei Hamakawa; Tomoya Kashimata; Masaya Yamasaki; Kosuke Tatsumura (CoRR, 2025)

Real-Time Black-Box Optimization for Dynamic Discrete Environments Using Embedded Ising Machines. - Tomoya Kashimata; Yohei Hamakawa; Masaya Yamasaki; Kosuke Tatsumura (CoRR, 2025)