FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. - Kentaro Orimo; Kota Ando; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (ReConFig, 2016)

Accelerating deep learning by binarized hardware. - Shinya Takamaeda-Yamazaki; Kodai Ueyoshi; Kota Ando; Ryota Uematsu; Kazutoshi Hirose; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (APSIPA, 2017)

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. - Kazutoshi Hirose; Ryota Uematsu; Kota Ando; Kentaro Orimo; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (CANDAR, 2017)

Exploring optimized accelerator design for binarized convolutional neural networks. - Kodai Ueyoshi; Kota Ando; Kentaro Orimo; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (IJCNN, 2017)

In-memory area-efficient signal streaming processor design for binary neural networks. - Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Kota Ando; Kodai Ueyoshi; Kazutoshi Hirose; Kentaro Orimo; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (MWSCAS, 2017)

Quantization Error-Based Regularization in Neural Networks. - Kazutoshi Hirose; Kota Ando; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (SGAI Conf., 2017)

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. - Kota Ando; Kodai Ueyoshi; Yuka Oba; Kazutoshi Hirose; Ryota Uematsu; Takumi Kudo; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (FPT, 2018)

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Junichiro Kadomoto; Tomoki Miyata; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (ISSCC, 2018)

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. - Takumi Kudo; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Ryota Uematsu; Yuka Oba; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (MCSoC, 2018)

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. - Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2018)

DeltaNet: Differential Binary Neural Network. - Yuka Oba; Kota Ando; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (ASAP, 2019)

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. - Kota Ando; Kodai Ueyoshi; Yuka Oba; Kazutoshi Hirose; Ryota Uematsu; Takumi Kudo; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (IEICE Trans. Inf. Syst., 2019)

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2019)

ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. - Junnosuke Suzuki; Kota Ando; Kazutoshi Hirose; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (CANDAR, 2020)

A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. - Kota Shiba; Tatsuo Omori; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Masato Motomura; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2020)

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. - Kasho Yamamoto; Kota Ando; Normann Mertig; Takashi Takemoto; Masanao Yamaoka; Hiroshi Teramoto; Akira Sakai; Shinya Takamaeda-Yamazaki; Masato Motomura (ISSCC, 2020)

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. - Kota Ando; Jaehoon Yu; Kazutoshi Hirose; Hiroki Nakahara; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (HCS, 2021)

ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. - Junnosuke Suzuki; Tomohiro Kaneko; Kota Ando; Kazutoshi Hirose; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (Int. J. Netw. Comput., 2021)

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. - Kasho Yamamoto; Kazushi Kawamura; Kota Ando; Normann Mertig; Takashi Takemoto; Masanao Yamaoka; Hiroshi Teramoto; Akira Sakai; Shinya Takamaeda-Yamazaki; Masato Motomura (IEEE J. Solid State Circuits, 2021)

Multicoated Supermasks Enhance Hidden Networks. - Yasuyuki Okoshi; Ángel López García-Arias; Kazutoshi Hirose; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (ICML, 2022)

APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control. - Daiki Okonogi; Satoru Jimbo; Kota Ando; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (IPDPS Workshops, 2022)

Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. - Kazutoshi Hirose; Jaehoon Yu; Kota Ando; Yasuyuki Okoshi; Ángel López García-Arias; Junnosuke Suzuki; Thiem Van Chu; Kazushi Kawamura; Masato Motomura (ISSCC, 2022)

A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers. - Satoru Jimbo; Daiki Okonogi; Kota Ando; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (IEICE Trans. Inf. Syst., 2022)

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. - Kazushi Kawamura; Jaehoon Yu; Daiki Okonogi; Satoru Jimbo; Genta Inoue; Akira Hyodo; Ángel López García-Arias; Kota Ando; Bruno Hideki Fukushima-Kimura; Ryota Yasudo; Thiem Van Chu; Masato Motomura (ISSCC, 2023)

Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (VLSI Technology and Circuits, 2023)

TT-MLP: Tensor Train Decomposition on Deep MLPs. - Jiale Yan; Kota Ando; Jaehoon Yu; Masato Motomura (IEEE Access, 2023)

A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems. - Daiki Okonogi; Satoru Jimbo; Kota Ando; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (IEICE Trans. Inf. Syst., 2023)

Edge AI Online Training Architecture Using Multi-Phase-Quantization Optimizer. - Itsuki Akeno; Hiiro Yamazaki; Tetsuya Asai; Kota Ando (IJCNN, 2024)

Out-of-distribution Data Detection using Bayesian Convolutional Neural Network with Variational Inference. - Koki Minagawa; Taisei Saito; Sena Kojima; Kota Ando; Tetsuya Asai (IJCNN, 2024)

A Stacked FPGA utilizing 3D-SRAM with Latency Optimization. - Ryo Takahashi; Kota Ando; Hiroki Nakahara (MCSoC, 2024)

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (IEEE Access, 2024)

Extending Binary Neural Networks to Bayesian Neural Networks with Probabilistic Interpretation of Binary Weights. - Taisei Saito; Kota Ando; Tetsuya Asai (IEICE Trans. Inf. Syst., 2024)

SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA. - Yuki Abe; Kohei Nishida; Kota Ando; Tetsuya Asai (Int. J. Parallel Emergent Distributed Syst., 2024)