A 120-MHz BiCMOS superscalar RISC processor. - Shigeya Tanaka; Takashi Hotta; Fumio Murabayashi; Hiromichi Yamada; Shoji Yoshida; Kotaro Shimamura; Koyo Katsura; Tadaaki Bandoh; Koichi Ikeda; Kenji Matsubara; Kouji Saitou; Tetsuo Nakano; et al. (IEEE J. Solid State Circuits, 1994)

A superscalar RISC processor with pseudo vector processing feature. - Kotaro Shimamura; Shigeya Tanaka; Tetsuya Shimomura; Takashi Hotta; Eiki Kamada; Hideo Sawamoto; Teruhisa Shimizu; Kisaburo Nakazawa (ICCD, 1995)

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor. - Fumio Murabayashi; Tatsumi Yamauchi; Hiromichi Yamada; Takahiro Nishiyama; Kotaro Shimamura; Shigeya Tanaka; Takashi Hotta; Teruhisa Shimizu; Hideo Sawamoto (IEEE J. Solid State Circuits, 1996)

A Triple Redundant Controller which Adopts the Time-Sharing Fault Recovery Method and its Application to a Power Converter Controller. - Kotaro Shimamura; Yuichiro Morita; Yoshitaka Takahashi; Takashi Hotta; Shigeta Ueda; Mikiya Nohara; Mitsuyasu Kido; Seji Tanaka; Kazuhiro Imaie; Koji Sakamoto; Tatsuhito Nakajima (IEEE Real Time Technology and Applications Symposium, 1998)

A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature. - Kotaro Shimamura; Takeshi Takehara; Yosuke Shima; Kunihiko Tsunedomi (PRDC, 2006)

DART: Dependable VLSI test architecture and its implementation. - Yasuo Sato; Seiji Kajihara; Tomokazu Yoneda; Kazumi Hatayama; Michiko Inoue; Yukiya Miura; Satosni Untake; Takumi Hasegawa; Motoyuki Sato; Kotaro Shimamura (ITC, 2012)

Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator. - Kotaro Shimamura; Naohiro Ikeda (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs. - Yusuke Kanno; Tadanobu Toba; Kotaro Shimamura; Nobuyasu Kanekawa (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Measurement Results of Real Circuit Delay Degradation under Realistic Workload. - Kotaro Shimamura; Takeshi Takehara; Naohiro Ikeda (IPSJ Trans. Syst. LSI Des. Methodol., 2023)

FS-Boost: Communication-Efficient Federated Subtree-Based Gradient Boosting Decision Trees. - Kotaro Shimamura; Shinya Takamaeda-Yamazaki (CCNC, 2024)

Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-Scalar Multiplication. - Ayumi Ohno; Kotaro Shimamura; Shinya Takamaeda-Yamazaki (COOL CHIPS, 2025)

Exploring the Versal AI Engine for 3D Gaussian Splatting. - Kotaro Shimamura; Ayumi Ohno; Shinya Takamaeda-Yamazaki (COOL CHIPS, 2025)