Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs. - Kouichi Kanda; Kouichi Nose; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEEE J. Solid State Circuits, 2001)

90% write power-saving SRAM using sense-amplifying memory cell. - Kouichi Kanda; Hattori Sadaaki; Takayasu Sakurai (IEEE J. Solid State Circuits, 2004)

Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS). - Koichi Ishida; Kouichi Kanda; Atit Tamtrakarn; Hiroshi Kawaguchi 001; Takayasu Sakurai (ISCAS (4), 2005)

Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's. - Kyeong-Sik Min; Kouichi Kanda; Hiroshi Kawaguchi 001; Kenichi Inagaki; Fayez Robert Saliba; Hoon-Dae Choi; Hyun-Young Choi; Daejeong Kim; Dong Myong Kim; Takayasu Sakurai (IEICE Trans. Electron., 2005)

Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. - Hirotaka Tamura; Masaya Kibune; Hisakatsu Yamaguchi; Kouichi Kanda; Kohtaroh Gotoh; Hideki Ishida; Junji Ogawa (IEICE Trans. Electron., 2006)

Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS). - Koichi Ishida; Kouichi Kanda; Atit Tamtrakarn; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEEE J. Solid State Circuits, 2006)

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. - Yasuo Hidaka; Weixin Gai; Akira Hattori; Takeshi Horie; Jian Jiang; Kouichi Kanda; Yoichi Koyanagi; Satoshi Matsubara; Hideki Osone (ISSCC, 2007)

18-GHz Clock Distribution Using a Coupled VCO Array. - Takayuki Shibasaki; Hirotaka Tamura; Kouichi Kanda; Hisakatsu Yamaguchi; Junji Ogawa; Tadahiro Kuroda (IEICE Trans. Electron., 2007)

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. - Takayuki Shibasaki; Hirotaka Tamura; Kouichi Kanda; Hisakatsu Yamaguchi; Junji Ogawa; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2008)

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (ISSCC, 2009)

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (IEEE J. Solid State Circuits, 2009)

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS. - Keita Takatsu; Hirotaka Tamura; Takuji Yamamoto; Yoshiyasu Doi; Kouichi Kanda; Takayuki Shibasaki; Tadahiro Kuroda (CICC, 2010)

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. - Nikola Nedovic; Anders Kristensson; Samir Parikh; Subodh M. Reddy; Scott McLeod; Nestoras Tzartzanis; Kouichi Kanda; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Satoshi Ide; et al. (IEEE J. Solid State Circuits, 2010)

A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range. - Keita Takatsu; Hirotaka Tamura; Takuji Yamamoto; Yoshiyasu Doi; Kouichi Kanda; Takayuki Shibasaki; Tadahiro Kuroda (IEICE Trans. Electron., 2011)

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets. - Kouichi Kanda; Yoichi Kawano; Takao Sasaki; Noriaki Shirai; Tetsuro Tamura; Shigeaki Kawai; Masahiro Kudo; Tomotoshi Murakami; Hiroyuki Nakamoto; Nobumasa Hasegawa; Hideki Kano; Nobuhiro Shimazui; et al. (ISSCC, 2012)

9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications. - Maja Vidojkovic; Xiongchuan Huang; Xiaoyan Wang 002; Cui Zhou; Ao Ba; Maarten Lont; Yao-Hong Liu; Pieter Harpe; Ming Ding 003; Ben Busze; Nauman F. Kiyani; Kouichi Kanda; et al. (ISSCC, 2014)

Radio channel characterization for 400 MHz implanted devices. - Hans W. Pflug; Hubregt J. Visser; Nauman F. Kiyani; Guido Dolmans; Kathleen Philips; Kouichi Kanda; Makoto Hamaminato; Shoichi Masui (WCNC, 2014)

A 3.5mW 315/400MHz IEEE802.15.6/proprietary mode digitally-tunable radio SoC with integrated digital baseband and MAC processor in 40nm CMOS. - Christian Bachmann; Maja Vidojkovic; Xiongchuan Huang; Maarten Lont; Yao-Hong Liu; Ming Ding 003; Benjamin Busze; Jordy Gloudemans; Hans Giesen; Adnane Sbai; Gert-Jan van Schaik; Nauman F. Kiyani; et al. (VLSIC, 2015)

A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications. - Ao Ba; Maja Vidojkovic; Kouichi Kanda; Nauman F. Kiyani; Maarten Lont; Xiongchuan Huang; Xiaoyan Wang 002; Cui Zhou; Yao-Hong Liu; Ming Ding 003; Benjamin Busze; Shoichi Masui; et al. (IEEE J. Biomed. Health Informatics, 2015)

A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems. - Mohammad Bagherbeik; Parastoo Ashtari; Seyed Farzad Mousavi; Kouichi Kanda; Hirotaka Tamura; Ali Sheikholeslami (PPSN (1), 2020)

MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA. - Mohammad Bagherbeik; Wentao Xu; Seyed Farzad Mousavi; Kouichi Kanda; Hirotaka Tamura; Ali Sheikholeslami (FPGA, 2022)

MAQO: A Scalable Many-Core Annealer for Quadratic Optimization. - Mohammad Bagherbeik; Wentao Xu; Seyed Farzad Mousavi; Kouichi Kanda; Hirotaka Tamura; Ali Sheikholeslami (VLSI Technology and Circuits, 2022)

Digital Annealing Engine for High-speed Solving of Constrained Binary Quadratic Problems on Multiple GPUs. - Kentaro Katayama; Noboru Yoneoka; Kouichi Kanda; Hirotaka Tamura; Hiroshi Nakayama; Yasuhiro Watanabe (ICCE, 2024)