A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect. - Yoichiro Kurita; Koji Soejima; Katsumi Kikuchi; Masatake Takahashi; Masamoto Tago; Masahiro Koike; Koujirou Shibuya; Shintaro Yamamichi; Masaya Kawano (IEICE Trans. Electron., 2009)