A specified delay accomplishing clock router using multiple layers. - Mitsuho Seki; Kenji Inoue; Kazuo Kato; Kouki Tsurusaki; Shin'ichi Fukasawa; Hitoshi Sasaki; Mutsuhito Aizawa (ICCAD, 1994)

A practical clock router that accounts for the capacitance derived from parallel and cross segments. - Mitsuho Seki; Kazuo Kato; S. Kobayashi; Kouki Tsurusaki (EURO-DAC, 1996)