An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. - Mitsuo Ikeda; Toshio Kondo; Koyo Nitta; Kazuhito Suguri; Takeshi Yoshitome; Toshihiro Minami; Jiro Naganuma; Takeshi Ogura (DATE, 1999)

SuperENC: MPEG-2 video encoder chip. - Mitsuo Ikeda; Toshio Kondo; Koyo Nitta; Kazuhito Suguri; Takeshi Yoshitome; Toshihiro Minami; Hiroe Iwasaki; Katsuyuki Ochiai; Jiro Naganuma; Makoto Endo; Yutaka Tashiro; Hiroshi Watanabe 005; et al. (IEEE Micro, 1999)

A 4: 2: 2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI. - Takeshi Yoshitome; Toshihiro Minami; Mitsuo Ikeda; Koyo Nitta; Kazuhito Suguri (IEEE Trans. Consumer Electron., 1999)

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. - Hiroe Iwasaki; Jiro Naganuma; Koyo Nitta; Ken Nakamura; Takeshi Yoshitome; Mitsuo Ogura; Yasuyuki Nakajima; Yutaka Tashiro; Takayuki Onishi; Mitsuo Ikeda; Makoto Endo (DATE, 2003)

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. - Hiroe Iwasaki; Jiro Naganuma; Koyo Nitta; Ken Nakamura; Takeshi Yoshitome; Mitsuo Ogura; Yasuyuki Nakajima; Yutaka Tashiro; Takayuki Onishi; Mitsuo Ikeda; Toshihiro Minami; Makoto Endo; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI. - Takayuki Onishi; Takashi Sano 001; Koyo Nitta; Mitsuo Ikeda; Jiro Naganuma (ISCAS, 2008)

MVC real-time video encoder for full-HDTV 3D video. - Mitsuo Ikeda; Takayuki Onishi; Takashi Sano 001; Atsushi Sagata; Hiroe Iwasaki; Yasuyuki Nakajima; Koyo Nitta; Yasuko Takahashi; Kazuya Yokohari; Daisuke Kobayashi; Kazuto Kamikura; Hirohisa Jozawa (ICCE, 2012)

An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures. - Koyo Nitta; Hiroe Iwasaki; Takayuki Onishi; Takashi Sano 001; Atsushi Sagata; Yasuyuki Nakajima; Minoru Inamori; Ryuichi Tanida; Atsushi Shimizu; Ken Nakamura; Mitsuo Ikeda; Jiro Naganuma (IEICE Trans. Electron., 2012)

Residue role assignment based transform partition predetermination on HEVC. - Jia Su; Koyo Nitta; Mitsuo Ikeda; Atsushi Shimizu (ICIP, 2013)

Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure. - Hiroe Iwasaki; Takayuki Onishi; Ken Nakamura; Koyo Nitta; Takashi Sano 001; Yukikuni Nishida; Kazuya Yokohari; Jia Su; Naoki Ono; Ritsu Kusaba; Atsushi Sagata; Mitsuo Ikeda; et al. (Hot Chips Symposium, 2015)

Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability. - Takayuki Onishi; Takashi Sano 001; Yukikuni Nishida; Kazuya Yokohari; Jia Su; Ken Nakamura; Koyo Nitta; Kimiko Kawashima; Jun Okamoto; Naoki Ono; Ritsu Kusaba; Atsushi Sagata; et al. (VLSIC, 2015)

Motion Estimation and Compensation Hardware Architecture with Hierarchy of Flexibility in Video Encoder LSIs. - Koyo Nitta (2015)

Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane. - Koji Yamazaki; Yuta Ukon; Shuhei Yoshida; Saki Hatta; Yusuke Sekihara; Shoko Ohteru; Tomoaki Kawamura; Takahiro Hatano; Koyo Nitta; Akihiko Miyazaki (HPSR, 2018)

Video Service Function Chaining with a Real-time Packet Reordering Circuit. - Yuta Ukon; Koji Yamazaki; Koyo Nitta (ISCAS, 2018)

A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K. - Takayuki Onishi; Takashi Sano 001; Yukikuni Nishida; Kazuya Yokohari; Ken Nakamura; Koyo Nitta; Kimiko Kawashima; Jun Okamoto; Naoki Ono; Atsushi Sagata; Hiroe Iwasaki; Mitsuo Ikeda; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. - Ken Nakamura; Yuya Omori; Daisuke Kobayashi; Tatsuya Osawa; Takayuki Onishi; Koyo Nitta; Hiroe Iwasaki; Atsushi Shimizu (COOL CHIPS, 2019)

FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing. - Shuhei Yoshida; Yuta Ukon; Shoko Ohteru; Hiroyuki Uzawa; Namiko Ikeda; Koyo Nitta (ASAP, 2020)

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. - Ken Nakamura; Daisuke Kobayashi; Yuya Omori; Tatsuya Osawa; Takayuki Onishi; Koyo Nitta; Hiroe Iwasaki (IEICE Trans. Electron., 2020)

Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture. - Yuta Ukon; Koji Yamazaki; Koyo Nitta (IEICE Trans. Commun., 2020)

Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems. - Saki Hatta; Nobuyuki Tanaka; Hiroyuki Uzawa; Koyo Nitta (IEICE Trans. Commun., 2021)

A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation. - Hiroyuki Uzawa; Kazuhiko Terada; Koyo Nitta (IEICE Trans. Commun., 2021)

FPGA-based network microburst analysis system with efficient packet capturing. - Shuhei Yoshida; Yuta Ukon; Shoko Ohteru; Hiroyuki Uzawa; Namiko Ikeda; Koyo Nitta (JOCN, 2021)

An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. - Ken Nakamura; Yuya Omori; Daisuke Kobayashi; Koyo Nitta; Kimikazu Sano; Masayuki Sato 001; Hiroe Iwasaki; Hiroaki Kobayashi (COOL CHIPS, 2022)

OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. - Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Hiroe Iwasaki; Daisuke Kobayashi; Yuya Omori; Ken Nakamura; Koyo Nitta; Kimikazu Sano (MWSCAS, 2022)

High-definition technology of AI inference scheme for object detection on edge/terminal. - Hiroyuki Uzawa; Shuhei Yoshida; Yukou Iinuma; Saki Hatta; Daisuke Kobayashi; Yuya Omori; Yusuke Horishita; Ken Nakamura; Shuichi Takada; Hassan Toorabally; Koyo Nitta; Koji Yamazaki; et al. (IEICE Electron. Express, 2023)

An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. - Ken Nakamura; Yuya Omori; Daisuke Kobayashi; Koyo Nitta; Kimikazu Sano; Masayuki Sato 001; Hiroe Iwasaki; Hiroaki Kobayashi (IEICE Trans. Electron., 2023)

Video Transfer Method Suitable for Object Detection in the Cloud. - Mamoru Shirahase; Koyo Nitta; Yusuke Horishita; Yuya Omori; Daisuke Kobayashi; Ken Nakamura (ICCE, 2025)