Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Periphery VDD Collapse in SRAMs. - Krashna Nand Mishra; Ruchin Jain; Shailendra Sharad; Ravindra Shrivastava (VLSID, 2019)

Creating Fastest Self timing Reference Path for High Speed Memory Designs. - Krashna Nand Mishra; Yogeshbhai Vallabhbhai Patel (VLSID, 2021)