Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. - Mustafa Badaroglu; Kris Tiri; Stéphane Donnay; Piet Wambacq; Hugo De Man; Ingrid Verbauwhede; Georges G. E. Gielen (DAC, 2002)

Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology. - Kris Tiri; Ingrid Verbauwhede (CHES, 2003)

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. - Mustafa Badaroglu; Lakshmanan Balasubramanian; Kris Tiri; Vincent Gravot; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (ESSCIRC, 2003)

Place and Route for Secure Standard Cell Design. - Kris Tiri; Ingrid Verbauwhede (CARDIS, 2004)

Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques. - Yusuke Matsuoka; Patrick Schaumont; Kris Tiri; Ingrid Verbauwhede (CASES, 2004)

A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. - Kris Tiri; Ingrid Verbauwhede (DATE, 2004)

Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis]. - Kris Tiri; Ingrid Verbauwhede (ESSCIRC, 2004)

Secure Logic Synthesis. - Kris Tiri; Ingrid Verbauwhede (FPL, 2004)

A Dynamic and Differential CMOS Logic Style to Resist Power and Timing Attacks on Security IC's. - Kris Tiri; Ingrid Verbauwhede (IACR Cryptol. ePrint Arch., 2004)

Charge Recycling Sense Amplifier Based Logic: Securing Low Power Security IC's against Differential Power Analysis. - Kris Tiri; Ingrid Verbauwhede (IACR Cryptol. ePrint Arch., 2004)

Synthesis of Secure FPGA Implementations. - Kris Tiri; Ingrid Verbauwhede (IACR Cryptol. ePrint Arch., 2004)

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. - Mustafa Badaroglu; Geert Van der Plas; Piet Wambacq; Lakshmanan Balasubramanian; Kris Tiri; Ingrid Verbauwhede; Stéphane Donnay; Georges G. E. Gielen; Hugo J. De Man (IEEE J. Solid State Circuits, 2004)

Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. - Kris Tiri; David D. Hwang; Alireza Hodjat; Bo-Cheng Lai; Shenglin Yang; Patrick Schaumont; Ingrid Verbauwhede (CHES, 2005)

A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. - Kris Tiri; David D. Hwang; Alireza Hodjat; Bo-Cheng Lai; Shenglin Yang; Patrick Schaumont; Ingrid Verbauwhede (DAC, 2005)

Simulation models for side-channel information leaks. - Kris Tiri; Ingrid Verbauwhede (DAC, 2005)

Design Method for Constant Power Consumption of Differential Logic Circuits. - Kris Tiri; Ingrid Verbauwhede (DATE, 2005)

A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. - Kris Tiri; Ingrid Verbauwhede (DATE, 2005)

A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology. - Alireza Hodjat; David Hwang 001; Bo-Cheng Lai; Kris Tiri; Ingrid Verbauwhede (ACM Great Lakes Symposium on VLSI, 2005)

Side-Channel Leakage Tolerant Architectures. - Kris Tiri; Patrick Schaumont; Ingrid Verbauwhede (ITNG, 2006)

Changing the Odds Against Masked Logic. - Kris Tiri; Patrick Schaumont (Selected Areas in Cryptography, 2006)

Securing Embedded Systems. - David Hwang 001; Patrick Schaumont; Kris Tiri; Ingrid Verbauwhede (IEEE Secur. Priv., 2006)

AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. - David D. Hwang; Kris Tiri; Alireza Hodjat; Bo-Cheng Lai; Shenglin Yang; Patrick Schaumont; Ingrid Verbauwhede (IEEE J. Solid State Circuits, 2006)

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. - Mustafa Badaroglu; Kris Tiri; Geert Van der Plas; Piet Wambacq; Ingrid Verbauwhede; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A digital design flow for secure integrated circuits. - Kris Tiri; Ingrid Verbauwhede (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Masking and Dual-Rail Logic Don't Add Up. - Patrick Schaumont; Kris Tiri (CHES, 2007)

Side-Channel Attack Pitfalls. - Kris Tiri (DAC, 2007)

An Analytical Model for Time-Driven Cache Attacks. - Kris Tiri; Onur Aciiçmez; Michael Neve; Flemming Andersen (FSE, 2007)

On the complexity of side-channel attacks on AES-256 - methodology and quantitative results on cache attacks. - Michael Neve; Kris Tiri (IACR Cryptol. ePrint Arch., 2007)

Side-Channel Resistant Circuit Styles and Associated IC Design Flow. - Kris Tiri (Secure Integrated Circuits and Systems, 2010)