Formal Verification Aware Redundant Sequential Logic Optimization to Improve Design Utilization. - Rushabh Shah; Krishna Agrawal (ISQED, 2021)

Automated Debugger for Optimum Physical Clock Structure Targeting Minimal Latency. - Rushabh Shah; Krishna Agrawal; G. Anjaneyulu; Vishnu Bhaskari (VLSID, 2022)

Dequeue Rate-Agnostic Switch Buffer Sharing through Packet Queueing Delay. - Krishna Agrawal; Vamsi Addanki; Habib Mostafaei (StudentWorkshop@CoNEXT, 2024)