Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossover below 2.5-V supply. - Rosalyn B. Ritts; Prasad A. Raje; James D. Plummer; Krishna C. Saraswat; Kit M. Cham (IEEE J. Solid State Circuits, 1991)

Flexible Relation: An Approach for Integrating Data from Multiple, Possibly Inconsistent Databases. - Shailesh Agarwal; Arthur M. Keller; Gio Wiederhold; Krishna Saraswat (ICDE, 1995)

Multiple Si layer ICs: motivation, performance analysis, and design implications. - Shukri J. Souri; Kaustav Banerjee; Amit Mehrotra; Krishna Saraswat (DAC, 2000)

Performance analysis and technology of 3-D ICs. - Krishna Saraswat; Shukri J. Souri; Kaustav Banerjee; Pawan Kapur (SLIP, 2000)

Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. - TingYen Chiang; Kaustav Banerjee; Krishna Saraswat (ICCAD, 2001)

Reliability Studies on Multilevel Interconnection with Intermetal Dielectric Air Gaps. - Valeriy Sukharev; Ben P. Shieh; Ratan K. Choudhury; Chong W. Park; Krishna C. Saraswat (Microelectron. Reliab., 2001)

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. - Kaustav Banerjee; Shukri J. Souri; Pawan Kapur; Krishna C. Saraswat (Proc. IEEE, 2001)

Interconnect limits on gigascale integration (GSI) in the 21st century. - Jeffery A. Davis; Raguraman Venkatesan; Alan Kaloyeros; Michael Beylansky; Shukri J. Souri; Kaustav Banerjee; Krishna C. Saraswat; Arifur Rahman; Rafael Reif; James D. Meindl (Proc. IEEE, 2001)

Power estimation in global interconnects and its reduction using a novel repeater optimization methodology. - Pawan Kapur; Gaurav Chandra; Krishna Saraswat (DAC, 2002)

Performance Limitations of Devices and Interconnects and Possible Alternatives for Nanoelectronics. - Krishna Saraswat (ISQED, 2004)

Self-consistent power/performance/reliability analysis for copper interconnects. - Bipin Rajendran; Pawan Kapur; Krishna Saraswat; R. Fabian W. Pease (SLIP, 2004)

Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects. - Hoyeol Cho; Kyung-Hoae Koo; Pawan Kapur; Krishna Saraswat (SLIP, 2007)

Performance comparison between copper, carbon nanotube, and optical interconnects. - Krishna Saraswat; Hoyeol Cho; Pawan Kapur; Kyung-Hoae Koo (ISCAS, 2008)

Performance comparison of cu/low-k, carbon nanotube, and optics for on-chip and off-chip interconnects. - Krishna Saraswat (SLIP, 2009)

Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs. - Chia-Hsin Owen Chen; Niket Agarwal; Tushar Krishna; Kyung-Hoae Koo; Li-Shiuan Peh; Krishna Saraswat (NOCS, 2010)

50GHz Ge waveguide electro-absorption modulator integrated in a 220nm SOI photonics platform. - Shashank Gupta; Srinivasan Ashwyn Srinivasan; Marianna Pantouvaki; Hongtao Chen; Peter Verheyen; Guy Lepage; Dries Van Thourhout; Gunther Roelkens; Krishna Saraswat; Philippe P. Absil; Joris Van Campenhout (OFC, 2015)

Keynote 1: The road to resilient computing in autonomous driving is paved with redundancy. - Nirmal R. Saxena; Sanu Mathew; Krishna Saraswat (IRPS, 2018)

3D-stacked Strained SiGe/Ge Gate-All-Around (GAA) Structure Fabricated by 3D Ge Condensation. - Junkyo Suh; Andrew C. Meng; Marc Jaikissoon; Michael Braun; Taeho R. Kim; Ann F. Marshall; Anahita Pakzad; Paul C. McIntyre; Krishna C. Saraswat (DRC, 2019)

Doped WS2 transistors with large on-off ratio and high on-current. - Aravindh Kumar; Koosha Nassiri Nazif; Pranav Ramesh; Krishna Saraswat (DRC, 2020)

Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties. - Lauren Hoang; Alwin Daus; Sumaiya Wahid; Jimin Kwon; Jung-Soo Ko; Shengjun Qin; Mahnaz Islam; Krishna C. Saraswat; H.-S. Philip Wong; Eric Pop (DRC, 2022)

Mobility Enhancement of Monolayer MoS2 Transistors using Tensile-Stressed Silicon Nitride Capping Layers. - Marc Jaikissoon; Jerry A. Yang; Kathryn M. Neilson; Eric Pop; Krishna C. Saraswat (DRC, 2022)

First Demonstration of Top-Gated ITO Transistors: Effect of Channel Passivation. - Sumaiya Wahid; Alwin Daus; Jimin Kwon; Shengjun Qin; Jung-Soo Ko; Krishna C. Saraswat; H.-S. Philip Wong; Eric Pop (DRC, 2022)

First Demonstration of Ge2Sb2Te5-Based Superlattice Phase Change Memory with Low Reset Current Density ( 3 MA/cm2) and Low Resistance Drift ( 0.002 at 105°C). - Asir Intisar Khan; Christopher Perez; Xiangjin Wu; Byoungjun Won; Kangsik Kim; Heungdong Kwon; Pranav Ramesh; Kathryn M. Neilson; Mehdi Asheghi; Krishna Saraswat; Zonghoon Lee; Il-Kwon Oh; et al. (VLSI Technology and Circuits, 2022)

Local Back-Gate Monolayer MoS2 Transistors with Channel Lengths Down to 50 nm and EOT ∼ 1 nm Showing Improved $I_{ text{on}}$ using Post-Metal Anneal. - Marc Jaikissoon; Jung-Soo Ko; Eric Pop; Krishna C. Saraswat (DRC, 2023)

Ultrathin Gate Dielectric Enabled by Nanofog Aluminum Oxide on Monolayer MoS2. - Jung-Soo Ko; Zichen Zhang 019; Sol Lee; Marc Jaikissoon; Robert K. A. Bennett; Kwanpyo Kim; Andrew C. Kummel; Prabhakar Bandaru; Eric Pop; Krishna C. Saraswat (ESSDERC, 2023)

Nanoscale MoS2 Transistors on Polyimide for Radio-Frequency Operation. - Eros Reato; P. Palacios; J. A. Yang; S. Wahid; Marc Jaikissoon; J.-S. Ko; Alwin Daus; M. Saeed; Krishna C. Saraswat; Renato Negra; Eric Pop; Max Christian Lemme (DRC, 2024)

Quantifying Defect-Mediated Electron Capture and Emission in Flexible Monolayer WS2 Field-Effect Transistors. - J. A. Yang; Eros Reato; Theresia Knobloch; J.-S. Ko; Z. Zhang; Andrew J. Mannix; Krishna Saraswat; Tibor Grasser; Max Christian Lemme; Eric Pop (DRC, 2024)

Achieving 1-nm-Scale Equivalent Oxide Thickness Top Gate Dielectric on Monolayer Transition Metal Dichalcogenide Transistors with CMOS-Friendly Approaches. - Jung-Soo Ko; Alex Shearer; Sol Lee; Kathryn M. Neilson; Marc Jaikissoon; Kwanpyo Kim; Stacey Bent; Krishna Saraswat; Eric Pop (VLSI Technology and Circuits, 2024)