The performance advantage of applying compression to the memory system. - Nihar R. Mahapatra; Jiangjiang Liu 002; Krishnan Sundaresan (MSP/ISMM, 2002)

Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. - Nihar R. Mahapatra; Jiangjiang Liu 002; Krishnan Sundaresan (ICCD, 2003)

The potential of compression to improve memory system performance, power consumption, and cost. - Nihar R. Mahapatra; Jiangjiang Liu 002; Krishnan Sundaresan; Srinivas Dangeti; Balakrishna V. Venkatrao (IPCCC, 2003)

Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses. - Jiangjiang Liu 002; Nihar R. Mahapatra; Krishnan Sundaresan (ISVLSI, 2003)

Code Compression Techniques for Embedded Systems and Their Effectiveness. - Krishnan Sundaresan; Nihar R. Mahapatra (ISVLSI, 2003)

Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study. - Jiangjiang Liu 002; Krishnan Sundaresan; Nihar R. Mahapatra (ICCD, 2004)

Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. - Krishnan Sundaresan; Nihar R. Mahapatra (HPCA, 2005)

Energy-Efficient Compressed Address Transmission. - Jiangjiang Liu 002; Krishnan Sundaresan; Nihar R. Mahapatra (VLSI Design, 2005)

An Accurate Energy and Thermal Model for Global Signal Buses. - Krishnan Sundaresan; Nihar R. Mahapatra (VLSI Design, 2005)

A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost. - Nihar R. Mahapatra; Jiangjiang Liu 002; Krishnan Sundaresan; Srinivas Dangeti; Balakrishna V. Venkatrao (J. Instr. Level Parallelism, 2005)

Value-based bit ordering for energy optimization of on-chip global signal buses. - Krishnan Sundaresan; Nihar R. Mahapatra (DATE, 2006)

Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction. - Jiangjiang Liu 002; Krishnan Sundaresan; Nihar R. Mahapatra (ACM Great Lakes Symposium on VLSI, 2006)

Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. - Jiangjiang Liu 002; Krishnan Sundaresan; Nihar R. Mahapatra (ICCD, 2006)

An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires. - Krishnan Sundaresan; Nihar R. Mahapatra (DAC, 2007)

Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. - Krishnan Sundaresan; Nihar R. Mahapatra (ISQED, 2008)