Large-swing CMOS buffer amplifier. - Krishnaswamy Nagaraj (IEEE J. Solid State Circuits, 1989)

Sampled-data and continuous-time squarers in MOS technology. - John M. Khoury; Krishnaswamy Nagaraj; James M. Trosino (IEEE J. Solid State Circuits, 1990)

A baseband codec for digital cellular telephony. - Kadaba R. Lakshmikumar; David W. Green; Krishnaswamy Nagaraj; King-Hon Lau; Oscar E. Agazzi; Jeffrey R. Barner; Reza S. Shariatdoust; Gene A. Wilson; Tuan N. Le; M. R. Dwarakanath; Jacques G. Ruch; Jit Kumar; et al. (IEEE J. Solid State Circuits, 1991)

A low supply voltage high PSRR voltage reference in CMOS process. - Khong-Meng Tham; Krishnaswamy Nagaraj (IEEE J. Solid State Circuits, 1995)

A 160-MHz analog equalizer for magnetic disk read Channel. - Sami Kiriaki; T. Lakshmi Viswanathan; Gennady Feygin; Robert Bogdan Staszewski; Richard Pierson; Bill Krenik; Michiel de Wit; Krishnaswamy Nagaraj (IEEE J. Solid State Circuits, 1997)

A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers. - Krishnaswamy Nagaraj; H. Scott Fetterman; Joseph Anidjar; Stephen H. Lewis; Robert G. Renninger (IEEE J. Solid State Circuits, 1997)

Modeling of accumulation MOS capacitors for analog design in digital VLSI processes. - Shanthi Pavan; Yannis P. Tsividis; Krishnaswamy Nagaraj (ISCAS (6), 1999)

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. - Krishnaswamy Nagaraj; David A. Martin; Mark A. Wolfe; Ranjan Chattopadhyay; Shanthi Pavan; Jason Cancio; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 2000)

Widely programmable high-frequency continuous-time filters in digital CMOS technology. - Shanthi Pavan; Yannis P. Tsividis; Krishnaswamy Nagaraj (IEEE J. Solid State Circuits, 2000)

A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. - Gennady Feygin; Krishnaswamy Nagaraj; Ranjan Chattopadhyay; R. Herrera; I. Papantonopoulos; David A. Martin; P. Wu; Shanthi Pavan (CICC, 2001)

Editorial. - Krishnaswamy Nagaraj (IEEE J. Solid State Circuits, 2004)

New Associate Editor. - Krishnaswamy Nagaraj (IEEE J. Solid State Circuits, 2005)

New Associate Editors. - Krishnaswamy Nagaraj (IEEE J. Solid State Circuits, 2007)

Message from the Outgoing Editor-in-Chief. - Krishnaswamy Nagaraj (IEEE J. Solid State Circuits, 2007)

A Two-Stage ADC Architecture With VCO-Based Second Stage. - Amit Kumar Gupta; Krishnaswamy Nagaraj; T. R. Viswanathan 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Novel fractional-n PLL Based on a Simple Reference Multiplier. - Xiao Pu 006; Krishnaswamy Nagaraj; Jacob A. Abraham; Axel Thomsen (J. Circuits Syst. Comput., 2012)

Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference. - Xiao Pu 006; Ajay Kumar; Krishnaswamy Nagaraj (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. - Krishnaswamy Nagaraj; Anant S. Kamath; Karthik Subburaj; Biman Chattopadhyay; Gopalkrishna Nayak; Satyasai Evani; Neeraj P. Nayak; Indu Prathapan; Frank Zhang; Baher Haroun (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC. - Amit Kumar Gupta; Krishnaswamy Nagaraj; T. R. Viswanathan 001 (MWSCAS, 2014)

Corrections to "Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference". - Xiao Pu 006; Ajay Kumar; Krishnaswamy Nagaraj (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An Embedded 65 nm CMOS Remote Temperature Sensor With Digital Beta Correction and Series Resistance Cancellation Achieving an Inaccuracy of 0.4°C (3σ) From - 40°C to 130°C. - Xiao Pu 006; Mikel Ash; Krishnaswamy Nagaraj; Joonsung Park; Steve Vu; Paul Kimelman; Sean de la Haye (IEEE J. Solid State Circuits, 2015)

An oxide electrothermal filter in standard CMOS. - Lorenzo Pedala; Ugur Sonmez; Fabio Sebastiano; Kofi A. A. Makinwa; Krishnaswamy Nagaraj; Joonsung Park (IEEE SENSORS, 2016)

A 12-/14-bit, 4/2MSPS, 0.085mm2 SAR ADC in 65nm using novel residue boosting. - Joonsung Park; Krishnaswamy Nagaraj; Mikel Ash; Ajay Kumar (CICC, 2017)

Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection. - Mehmet Ince; Ender Yilmaz; Wei Fu; Joonsung Park; Krishnaswamy Nagaraj; LeRoy Winemberg; Sule Ozev (ETS, 2019)

Fault-based Built-in Self-test and Evaluation of Phase Locked Loops. - Mehmet Ince; Ender Yilmaz; Wei Fu; Joonsung Park; Krishnaswamy Nagaraj; LeRoy Winemberg; Sule Ozev (ACM Trans. Design Autom. Electr. Syst., 2021)