A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter. - Jan A. Angevare; Kristof Blutman; Amir Zjajo; Nick van der Meijs (NORCHIP, 2013)

A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS. - Kristof Blutman; Jan A. Angevare; Amir Zjajo; Nick van der Meijs (ISCAS, 2014)

Lower power by voltage stacking: a fine-grained system design approach. - Kristof Blutman; Ajay Kapoor; Jacinto Garcia Martinez; Hamed Fatemi; José Pineda de Gyvez (DAC, 2016)

A microcontroller with 96% power-conversion efficiency using stacked voltage domains. - Kristof Blutman; Ajay Kapoor; Arjun Majumdar; Jacinto Garcia Martinez; Juan Diego Echeverri; Leo Sevat; Arnoud P. van der Wel; Hamed Fatemi; José Pineda de Gyvez; Kofi A. A. Makinwa (VLSI Circuits, 2016)

Floorplan and placement methodology for improved energy reduction in stacked power-domain design. - Kristof Blutman; Hamed Fatemi; Andrew B. Kahng; Ajay Kapoor; Jiajia Li 002; José Pineda de Gyvez (ASP-DAC, 2017)

A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling. - Kristof Blutman; Ajay Kapoor; Arjun Majumdar; Jacinto Garcia Martinez; Juan Diego Echeverri; Leo Sevat; Arnoud P. van der Wel; Hamed Fatemi; Kofi A. A. Makinwa; José Pineda de Gyvez (IEEE J. Solid State Circuits, 2017)

Logic Design Partitioning for Stacked Power Domains. - Kristof Blutman; Hamed Fatemi; Ajay Kapoor; Andrew B. Kahng; Jiajia Li 002; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2017)