An NTSC and PAL closed caption processor. - Sayan Teerapnyawatt; Krit Athikulwongse (FPL, 1997)

A study of Through-Silicon-Via impact on the 3D stacked IC layout. - Dae Hyun Kim 004; Krit Athikulwongse; Sung Kyu Lim (ICCAD, 2009)

Buffered clock tree sizing for skew minimization under power and thermal budgets. - Krit Athikulwongse; Xin Zhao 001; Sung Kyu Lim (ASP-DAC, 2010)

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. - Michael B. Healy; Krit Athikulwongse; Rohan Goel; Mohammad M. Hossain; Dae Hyun Kim 004; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Moongon Jung; Brian Ouellette; Mohit Pathak; et al. (CICC, 2010)

TSV stress aware timing analysis with applications to 3D-IC layout optimization. - Jae-Seok Yang; Krit Athikulwongse; Young-Joon Lee; Sung Kyu Lim; David Z. Pan (DAC, 2010)

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. - Krit Athikulwongse; Ashutosh Chakraborty; Jae-Seok Yang; David Z. Pan; Sung Kyu Lim (ICCAD, 2010)

Design for manufacturability and reliability for TSV-based 3D ICs. - David Z. Pan; Sung Kyu Lim; Krit Athikulwongse; Moongon Jung; Joydeep Mitra; Jiwoo Pak; Mohit Pathak; Jae-Seok Yang (ASP-DAC, 2012)

Exploiting die-to-die thermal coupling in 3D IC placement. - Krit Athikulwongse; Mohit Pathak; Sung Kyu Lim (DAC, 2012)

3D-MAPS: 3D Massively parallel processor with stacked memory. - Dae Hyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (ISSCC, 2012)

Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs. - Krit Athikulwongse; Dae Hyun Kim 004; Moongon Jung; Sung Kyu Lim (ASP-DAC, 2013)

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. - Krit Athikulwongse; Jae-Seok Yang; David Z. Pan; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout. - Dae Hyun Kim 004; Krit Athikulwongse; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement. - Krit Athikulwongse; Mongkol Ekpanyapong; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). - Daehyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (IEEE Trans. Computers, 2015)

Fast bidirectional shortest path on GPU. - Lalinthip Tangjittaweechai; Mongkol Ekpanyapong; Thaisiri Watewai; Krit Athikulwongse; Sung Kyu Lim; Adriano Tavares (IEICE Electron. Express, 2016)

Application Specific Architecture for Hardware Accelerating HOG-SVM to Achieve High Throughput on HD Frames. - Piyumal Ranawaka; Mongkol Ekpanyapong; Adriano Tavares; Jorge Cabral 001; Krit Athikulwongse; Vitor Alberto Silva (ASAP, 2019)

High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA. - Piyumal Ranawaka; Mongkol Ekpanyapong; Adriano Tavares; Mathew Dailey; Krit Athikulwongse; Vitor Alberto Silva (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Mapping the Physical and Dielectric Properties of Layered Soil Using Short-Time Matrix Pencil Method-Based Ground-Penetrating Radar. - Nattawat Chantasen; Akkarat Boonpoonga; Krit Athikulwongse; Kamol Kaemarungsi; Prayoot Akkaraekthalin (IEEE Access, 2020)

Improved Step Detection with Smartphone Handheld Mode Recognition. - Warnnaphorn Suksuganjana; Seksan Laitrakun; Krit Athikulwongse; Yuko Hara-Azumi; Somrudee Deepaisarn (KST, 2021)

Implementation of and Experimentation with Ground-Penetrating Radar for Real-Time Automatic Detection of Buried Improvised Explosive Devices. - Pachara Srimuk; Akkarat Boonpoonga; Kamol Kaemarungsi; Krit Athikulwongse; Sitthichai Dentri (Sensors, 2022)