SPERT: a VLIW/SIMD microprocessor for artificial neural network computations. - Krste Asanovic; James Beck; Brian Kingsbury; Phil Kohn; Nelson Morgan; John Wawrzynek (ASAP, 1992)

Designing A Connectionist Network Supercomputer. - Krste Asanovic; James Beck; Jerry Feldman; Nelson Morgan; John Wawrzynek (Int. J. Neural Syst., 1993)

The design of a neuro-microprocessor. - John Wawrzynek; Krste Asanovic; Nelson Morgan (IEEE Trans. Neural Networks, 1993)

Using simulations of reduced precision arithmetic to design a neuro-microprocessor. - Krste Asanovic; Nelson Morgan; John Wawrzynek (J. VLSI Signal Process., 1993)

SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training. - John Wawrzynek; Krste Asanovic; Brian Kingsbury; James Beck; David Johnson 001; Nelson Morgan (NIPS, 1995)

Spert-II: A Vector Microprocessor System. - John Wawrzynek; Krste Asanovic; Brian Kingsbury; David Johnson 001; James Beck; Nelson Morgan (Computer, 1996)

Using PHiPAC to speed error back-propagation learning. - Jeff A. Bilmes; Krste Asanovic; Chee-Whye Chin; James Demmel (ICASSP, 1997)

Intelligent RAM (IRAM): The Industrial Setting, Applications and Architectures. - David A. Patterson 001; Krste Asanovic; Aaron B. Brown; Richard Fromm; Jason Golbus; Benjamin Gribstad; Kimberly Keeton; Christoforos E. Kozyrakis; David R. Martin 001; Stylianos Perissakis; Randi Thomas; Noah Treuhaft; et al. (ICCD, 1997)

Optimizing Matrix Multiply Using PHiPAC: A Portable, High-Performance, ANSI C Coding Methodology. - Jeff A. Bilmes; Krste Asanovic; Chee-Whye Chin; James Demmel (International Conference on Supercomputing, 1997)

A Fast Kohonen Net Implementation for Spert-II. - Krste Asanovic (IWANN, 1997)

Scalable Processors in the Billion-Transistor Era: IRAM. - Christoforos E. Kozyrakis; Stylianos Perissakis; David A. Patterson 001; Thomas E. Anderson; Krste Asanovic; Neal Cardwell; Richard Fromm; Jason Golbus; Benjamin Gribstad; Kimberly Keeton; Randi Thomas; Noah Treuhaft; et al. (Computer, 1997)

Dynamic zero compression for cache energy reduction. - Luis Villa; Michael Zhang; Krste Asanovic (MICRO, 2000)

Energy-Efficient Register Access. - Jessica H. Tseng; Krste Asanovic (SBCCI, 2000)

Heads and tails: a variable-length instruction format supporting parallel fetch and decode. - Heidi Pan; Krste Asanovic (CASES, 2001)

Direct addressed caches for reduced power consumption. - Emmett Witchel; Samuel Larsen; C. Scott Ananian; Krste Asanovic (MICRO, 2001)

Multithreading decoupled architectures for complexity-effective general purpose computing. - Michael Sung; Ronny Krashinsky; Krste Asanovic (SIGARCH Comput. Archit. News, 2001)

Mondrian memory protection. - Emmett Witchel; Josh Cates; Krste Asanovic (ASPLOS, 2002)

Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. - Seongmoo Heo; Kenneth C. Barr; Mark Hampton; Krste Asanovic (ISCA, 2002)

Fine-grain CAM-tag cache resizing using miss tags. - Michael Zhang; Krste Asanovic (ISLPED, 2002)

Hardware Works, Software Doesn't: Enforcing Modularity with Mondriaan Memory Protection. - Emmett Witchel; Krste Asanovic (HotOS, 2003)

Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. - Jessica H. Tseng; Krste Asanovic (ISCA, 2003)

Reducing power density through activity migration. - Seongmoo Heo; Kenneth C. Barr; Krste Asanovic (ISLPED, 2003)

Power-optimal pipelining in deep submicron technology. - Seongmoo Heo; Krste Asanovic (ISLPED, 2004)

Cache Refill/Access Decoupling for Vector Machines. - Christopher Batten; Ronny Krashinsky; Steve Gerding; Krste Asanovic (MICRO, 2004)

The Vector-Thread Architecture. - Ronny Krashinsky; Christopher Batten; Mark Hampton; Steve Gerding; Brian Pharris; Jared Casper; Krste Asanovic (IEEE Micro, 2004)

Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. - Michael Zhang; Krste Asanovic (ISCA, 2005)

Replacing global wires with an on-chip network: a power analysis. - Seongmoo Heo; Krste Asanovic (ISLPED, 2005)

Accelerating Multiprocessor Simulation with a Memory Timestamp Record. - Kenneth C. Barr; Heidi Pan; Michael Zhang; Krste Asanovic (ISPASS, 2005)

Mondrix: memory isolation for linux using mondriaan memory protection. - Emmett Witchel; Junghwan Rhee; Krste Asanovic (SOSP, 2005)

Controlling program execution through binary instrumentation. - Heidi Pan; Krste Asanovic; Robert Cohn; Chi-Keung Luk (SIGARCH Comput. Archit. News, 2005)

A Speculative Control Scheme for an Energy-Efficient Banked Register Fil. - Jessica H. Tseng; Krste Asanovic (IEEE Trans. Computers, 2005)

Research accelerator for multiple processors. - David A. Patterson 001; Arvind 001; Krste Asanovic; Derek Chiou; James C. Hoe; Christos Kozyrakis; Shih-Lien Lu; Mark Oskin; Jan M. Rabaey; John Wawrzynek (Hot Chips Symposium, 2006)

Implementing virtual memory in a vector processor with software restart markers. - Mark Hampton; Krste Asanovic (ICS, 2006)

Branch trace compression for snapshot-based simulation. - Kenneth C. Barr; Krste Asanovic (ISPASS, 2006)

Accelerating architectural exploration using canonical instruction segments. - Rose F. Liu; Krste Asanovic (ISPASS, 2006)

METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors. - Jae W. Lee; Krste Asanovic (IEEE Real Time Technology and Applications Symposium, 2006)

Rethinking Hardware Support for Network Analysis and Intrusion Prevention. - Vern Paxson; Krste Asanovic; Sarang Dharmapurikar; John W. Lockwood; Ruoming Pang; Robin Sommer; Nicholas Weaver (HotSec, 2006)

Unbounded Transactional Memory. - C. Scott Ananian; Krste Asanovic; Bradley C. Kuszmaul; Charles E. Leiserson; Sean Lie (IEEE Micro, 2006)

Energy-aware lossless data compression. - Kenneth C. Barr; Krste Asanovic (ACM Trans. Comput. Syst., 2006)

Transactors for parallel hardware and software co-design. - Krste Asanovic (HLDVT, 2007)

Continual hashing for efficient fine-grain state inconsistency detection. - Jae W. Lee; Myron King; Krste Asanovic (ICCD, 2007)

RAMP: Research Accelerator for Multiple Processors. - John Wawrzynek; David A. Patterson 001; Mark Oskin; Shih-Lien Lu; Christoforos E. Kozyrakis; James C. Hoe; Derek Chiou; Krste Asanovic (IEEE Micro, 2007)

Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. - Seongmoo Heo; Ronny Krashinsky; Krste Asanovic (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Compiling for vector-thread architectures. - Mark Hampton; Krste Asanovic (CGO, 2008)

Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. - Christopher Batten; Ajay Joshi; Jason Orcutt; Anatoly Khilo; Benjamin Moss; Charles Holzwarth; Milos A. Popovic; Hanqing Li; Henry I. Smith; Judy L. Hoyt; Franz X. Kärtner; Rajeev J. Ram; et al. (Hot Interconnects, 2008)

MEMOCODE 2008 Co-Design Contest. - Patrick Schaumont; Krste Asanovic; James C. Hoe (MEMOCODE, 2008)

Implementing the scale vector-thread processor. - Ronny Krashinsky; Christopher Batten; Krste Asanovic (ACM Trans. Design Autom. Electr. Syst., 2008)

Designing multi-socket systems using silicon photonics. - Scott Beamer; Krste Asanovic; Christopher Batten; Ajay Joshi; Vladimir Stojanovic (ICS, 2009)

Silicon-photonic clos networks for global on-chip communication. - Ajay Joshi; Christopher Batten; Yong-Jin Kwon; Scott Beamer; Imran Shamim; Krste Asanovic; Vladimir Stojanovic (NOCS, 2009)

A view of the parallel computing landscape. - Krste Asanovic; Rastislav Bodík; James Demmel; Tony M. Keaveny; Kurt Keutzer; John Kubiatowicz; Nelson Morgan; David A. Patterson 001; Koushik Sen; John Wawrzynek; David Wessel; Katherine A. Yelick (Commun. ACM, 2009)

Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics. - Christopher Batten; Ajay Joshi; Jason Orcutt; Anatol Khilo; Benjamin Moss; Charles Holzwarth; Milos A. Popovic; Hanqing Li; Henry I. Smith; Judy L. Hoyt; Franz X. Kärtner; Rajeev J. Ram; et al. (IEEE Micro, 2009)

RAMP gold: an FPGA-based architecture simulator for multiprocessors. - Zhangxi Tan; Andrew Waterman; Rimas Avizienis; Yunsup Lee; Henry Cook; David A. Patterson 001; Krste Asanovic (DAC, 2010)

Re-architecting DRAM memory systems with monolithically integrated silicon photonics. - Scott Beamer; Chen Sun 003; Yong-Jin Kwon; Ajay Joshi; Christopher Batten; Vladimir Stojanovic; Krste Asanovic (ISCA, 2010)

A case for FAME: FPGA architecture model execution. - Zhangxi Tan; Andrew Waterman; Henry Cook; Sarah Bird; Krste Asanovic; David A. Patterson 001 (ISCA, 2010)

Composing parallel software efficiently with lithe. - Heidi Pan; Benjamin Hindman; Krste Asanovic (PLDI, 2010)

Guest Editors' Introduction: Hot Chips 21. - Krste Asanovic; Ralph Wittig (IEEE Micro, 2010)

Tessellation operating system: Building a real-time, responsive, high-throughput client OS for many-core architectures. - Juan A. Colmenares; Sarah Bird; Gage Eads; Steven A. Hofmeyr; Albert Kim; Rohit Poddar; Hilfi Alkaff; Krste Asanovic; John Kubiatowicz (Hot Chips Symposium, 2011)

The Maven vector-thread architecture. - Yunsup Lee; Rimas Avizienis; Alex Bishara; Richard Xia; Derek Lockhart; Christopher Batten; Krste Asanovic (Hot Chips Symposium, 2011)

Real-time Musical Applications on an Experimental Operating System for Multi-Core Processors. - Juan A. Colmenares; Ian Saxton; Eric Battenberg; Rimas Avizienis; Nils Peters; Krste Asanovic; John Kubiatowicz; David Wessel (ICMC, 2011)

Chisel: constructing hardware in a Scala embedded language. - Jonathan Bachrach; Huy Vo; Brian C. Richards; Yunsup Lee; Andrew Waterman; Rimas Avizienis; John Wawrzynek; Krste Asanovic (DAC, 2012)

GPUs as an opportunity for offloading garbage collection. - Martin Maas 001; Philip Reames; Jeffrey Morlan; Krste Asanovic; Anthony D. Joseph; John Kubiatowicz (ISMM, 2012)

Context-centric Security. - Mohit Tiwari; Prashanth Mohan; Andrew Osheroff; Hilfi Alkaff; Elaine Shi; Eric Love; Dawn Song; Krste Asanovic (HotSec, 2012)

Designing Chip-Level Nanophotonic Interconnection Networks. - Christopher Batten; Ajay Joshi; Vladimir Stojanovic; Krste Asanovic (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks. - Jae W. Lee; Man Cheuk Ng; Krste Asanovic (J. Parallel Distributed Comput., 2012)

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS. - Brian Zimmer; Seng Oon Toh; Huy Vo; Yunsup Lee; Olivier Thomas; Krste Asanovic; Borivoje Nikolic (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

PHANTOM: practical oblivious computation in a secure processor. - Martin Maas 001; Eric Love; Emil Stefanov; Mohit Tiwari; Elaine Shi; Krste Asanovic; John Kubiatowicz; Dawn Song (CCS, 2013)

Convergence and scalarization for data-parallel architectures. - Yunsup Lee; Ronny Krashinsky; Vinod Grover; Stephen W. Keckler; Krste Asanovic (CGO, 2013)

Tessellation: refactoring the OS around explicit resource containers with continuous adaptation. - Juan A. Colmenares; Gage Eads; Steven A. Hofmeyr; Sarah Bird; Miquel Moretó; David Chou; Brian Gluzman; Eric Roman; Davide B. Bartolini; Nitesh Mor; Krste Asanovic; John Kubiatowicz (DAC, 2013)

Welcome from general chairs. - Krste Asanovic; Jan-Willem van de Waerdt (Hot Chips Symposium, 2013)

Measuring the gap between programmable and fixed-function accelerators: A case study on speech recognition. - Yunsup Lee; David Sheffield; Andrew Waterman; Michael J. Anderson; Kurt Keutzer; Krste Asanovic (Hot Chips Symposium, 2013)

The RISC-V instruction set. - Andrew Waterman; Yunsup Lee; Rimas Avizienis; Henry Cook; David A. Patterson 001; Krste Asanovic (Hot Chips Symposium, 2013)

Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search. - Scott Beamer; Aydin Buluç; Krste Asanovic; David A. Patterson 001 (IPDPS Workshops, 2013)

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness. - Henry Cook; Miquel Moretó; Sarah Bird; Khanh Dao; David A. Patterson 001; Krste Asanovic (ISCA, 2013)

Direction-optimizing breadth-first search. - Scott Beamer; Krste Asanovic; David A. Patterson 001 (Sci. Program., 2013)

Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators. - Yunsup Lee; Rimas Avizienis; Alex Bishara; Richard Xia; Derek Lockhart; Christopher Batten; Krste Asanovic (ACM Trans. Comput. Syst., 2013)

A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators. - Yunsup Lee; Andrew Waterman; Rimas Avizienis; Henry Cook; Chen Sun 003; Vladimir Stojanovic; Krste Asanovic (ESSCIRC, 2014)

Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM. - Brian Zimmer; Olivier Thomas; Seng Oon Toh; Taylor Vincent; Krste Asanovic; Borivoje Nikolic (ESSDERC, 2014)

Author retrospective for optimizing matrix multiply using PHiPAC: a portable high-performance ANSI C coding methodology. - Jeff A. Bilmes; Krste Asanovic; Chee-Whye Chin; Jim Demmel (ICS 25th Anniversary, 2014)

Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures. - Yunsup Lee; Vinod Grover; Ronny Krashinsky; Mark Stephenson; Stephen W. Keckler; Krste Asanovic (MICRO, 2014)

DIABLO: A Warehouse-Scale Computer Network Simulator using FPGAs. - Zhangxi Tan; Zhenghao Qian; Xi Chen; Krste Asanovic; David A. Patterson 001 (ASPLOS, 2015)

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. - Yunsup Lee; Brian Zimmer; Andrew Waterman; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Henry Cook; Rimas Avizienis; et al. (Hot Chips Symposium, 2015)

Trash Day: Coordinating Garbage Collection in Distributed Systems. - Martin Maas 001; Tim Harris 001; Krste Asanovic; John Kubiatowicz (HotOS, 2015)

Locality Exists in Graph Processing: Workload Characterization on an Ivy Bridge Server. - Scott Beamer; Krste Asanovic; David A. Patterson 001 (IISWC, 2015)

GAIL: the graph algorithm iron law. - Scott Beamer; Krste Asanovic; David A. Patterson 001 (IA3@SC, 2015)

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (VLSIC, 2015)

The GAP Benchmark Suite. - Scott Beamer; Krste Asanovic; David A. Patterson 001 (CoRR, 2015)

Single-chip microprocessor that communicates directly using light. - Chen Sun 003; Mark T. Wade; Yunsup Lee; Jason S. Orcutt; Luca Alloatti; Michael Georgas; Andrew Waterman; Jeffrey M. Shainline; Rimas Avizienis; Sen Lin 002; Benjamin Moss; Rajesh Kumar; et al. (Nat., 2015)

Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors. - Ruzica Jevtic; Hanh-Phuc Le; Milovan Blagojevic; Stevo Bailey; Krste Asanovic; Elad Alon; Borivoje Nikolic (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Taurus: A Holistic Language Runtime System for Coordinating Distributed Managed-Language Applications. - Martin Maas 001; Krste Asanovic; Tim Harris 001; John Kubiatowicz (ASPLOS, 2016)

Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor. - Brian Zimmer; Pi-Feng Chiu; Borivoje Nikolic; Krste Asanovic (A-SSCC, 2016)

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. - Ben Keller; Martin Cochet; Brian Zimmer; Yunsup Lee; Milovan Blagojevic; Jaehwa Kwak; Alberto Puggelli; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (ESSCIRC, 2016)

Vector Processors for Energy-Efficient Embedded Systems. - Daniel Palmer Dabbelt; Colin Schmidt 001; Eric Love; Howard Mao; Sagar Karandikar; Krste Asanovic (MES@ISCA, 2016)

Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL. - Donggyu Kim; Adam M. Izraelevitz; Christopher Celio; Hokeun Kim; Brian Zimmer; Yunsup Lee; Jonathan Bachrach; Krste Asanovic (ISCA, 2016)

The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V. - Christopher Celio; Daniel Palmer Dabbelt; David A. Patterson 001; Krste Asanovic (CoRR, 2016)

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Steven Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (IEEE J. Solid State Circuits, 2016)

An Agile Approach to Building RISC-V Microprocessors. - Yunsup Lee; Andrew Waterman; Henry Cook; Brian Zimmer; Ben Keller; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Rimas Avizienis; et al. (IEEE Micro, 2016)

A Hardware Accelerator for Computing an Exact Dot Product. - Jack Koenig; David Biancolin; Jonathan Bachrach; Krste Asanovic (ARITH, 2017)

Return of the Runtimes: Rethinking the Language Runtime System for the Cloud 3.0 Era. - Martin Maas 001; Krste Asanovic; John Kubiatowicz (HotOS, 2017)

Cyclist: Accelerating hardware development. - Jonathan Bachrach; Albert Magyar; Daniel Palmer Dabbelt; Patrick Li; Richard Lin; Krste Asanovic (ICCAD, 2017)

Reducing Pagerank Communication via Propagation Blocking. - Scott Beamer; Krste Asanovic; David A. Patterson 001 (IPDPS, 2017)

Microprocessor chip with photonic I/O. - Chen Sun 003; Mark T. Wade; Yunsup Lee; Jason S. Orcutt; Luca Alloatti; Michael S. Georgas; Andrew S. Waterman; Jeffrey M. Shainline; Rimas R. Avizienis; Sen Lin 002; Benjamin R. Moss; Rajesh Kumar; et al. (OFC, 2017)

Distributed-Memory Breadth-First Search on Massive Graphs. - Aydin Buluç; Scott Beamer; Kamesh Madduri; Krste Asanovic; David A. Patterson 001 (CoRR, 2017)

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. - Ben Keller; Martin Cochet; Brian Zimmer; Jaehwa Kwak; Alberto Puggelli; Yunsup Lee; Milovan Blagojevic; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (IEEE J. Solid State Circuits, 2017)

Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction in a 28-nm RISC-V Processor. - Brian Zimmer; Pi-Feng Chiu; Borivoje Nikolic; Krste Asanovic (IEEE J. Solid State Circuits, 2017)

Generating the Next Wave of Custom Silicon. - Borivoje Nikolic; Elad Alon; Krste Asanovic (ESSCIRC, 2018)

DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles. - Donggyu Kim; Christopher Celio; Sagar Karandikar; David Biancolin; Jonathan Bachrach; Krste Asanovic (FPL, 2018)

An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS. - Pi-Feng Chiu; Christopher Celio; Krste Asanovic; David A. Patterson 001; Borivoje Nikolic (VLSI Circuits, 2018)

Open-Source EDA Tools and IP, A View from the Trenches. - Elad Alon; Krste Asanovic; Jonathan Bachrach; Borivoje Nikolic (DAC, 2019)

AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning. - Qijing Huang 001; Ameer Haj-Ali; William S. Moses; John Xiang; Ion Stoica; Krste Asanovic; John Wawrzynek (FCCM, 2019)

FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. - David Biancolin; Sagar Karandikar; Donggyu Kim; Jack Koenig; Andrew Waterman; Jonathan Bachrach; Krste Asanovic (FPGA, 2019)

FPGA Accelerated INDEL Realignment in the Cloud. - Lisa Wu 001; David Bruns-Smith; Frank A. Nothaft; Qijing Huang 001; Sagar Karandikar; Johnny Le; Andrew Lin; Howard Mao; Brendan Sweeney; Krste Asanovic; David A. Patterson 001; Anthony D. Joseph (HPCA, 2019)

Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration. - Qijing Huang 001; Christopher Yarp; Sagar Karandikar; Nathan Pemberton; Benjamin Brock; Liang Ma 003; Guohao Dai; Robert Quitt; Krste Asanovic; John Wawrzynek (ICCAD, 2019)

Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes. - Albert Magyar; David Biancolin; John Koenig; Sanjit Seshia; Jonathan Bachrach; Krste Asanovic (ICCAD, 2019)

Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection. - Donggyu Kim; Jerry Zhao; Jonathan Bachrach; Krste Asanovic (MICRO, 2019)

AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning. - Ameer Haj Ali; Qijing Huang 001; William S. Moses; John Xiang; Ion Stoica; Krste Asanovic; John Wawrzynek (CoRR, 2019)

Keystone: A Framework for Architecting TEEs. - Dayeol Lee; David Kohlbrenner; Shweta Shinde; Dawn Song; Krste Asanovic (CoRR, 2019)

Deep Reinforcement Learning in System Optimization. - Ameer Haj-Ali; Nesreen K. Ahmed; Theodore L. Willke; Joseph Gonzalez 001; Krste Asanovic; Ion Stoica (CoRR, 2019)

Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures. - Hasan Genc; Ameer Haj-Ali; Vighnesh Iyer; Alon Amid; Howard Mao; John Charles Wright; Colin Schmidt 001; Jerry Zhao; Albert J. Ou; Max Banister; Yakun Sophia Shao; Borivoje Nikolic; et al. (CoRR, 2019)

Sanctorum: A lightweight security monitor for secure enclaves. - Ilia A. Lebedev; Kyle Hogan; Jules Drean; David Kohlbrenner; Dayeol Lee; Krste Asanovic; Dawn Song; Srinivas Devadas (IACR Cryptol. ePrint Arch., 2019)

Co-design of deep neural nets and neural net accelerators for embedded vision applications. - Alon Amid; Kiseok Kwon; Amir Gholami; Bichen Wu; Krste Asanovic; Kurt Keutzer (IBM J. Res. Dev., 2019)

BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS. - Christopher Celio; Pi-Feng Chiu; Krste Asanovic; Borivoje Nikolic; David A. Patterson 001 (IEEE Micro, 2019)

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. - Sagar Karandikar; Howard Mao; Donggyu Kim; David Biancolin; Alon Amid; Dayeol Lee; Nathan Pemberton; Emmanuel Amaro; Colin Schmidt 001; Aditya Chopra; Qijing Huang 001; Kyle Kovacs; et al. (IEEE Micro, 2019)

A Hardware Accelerator for Tracing Garbage Collection. - Martin Maas 001; Krste Asanovic; John Kubiatowicz (IEEE Micro, 2019)

FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design. - Sagar Karandikar; Albert J. Ou; Alon Amid; Howard Mao; Randy H. Katz; Borivoje Nikolic; Krste Asanovic (ASPLOS, 2020)

NeuroVectorizer: end-to-end vectorization with deep reinforcement learning. - Ameer Haj-Ali; Nesreen K. Ahmed; Theodore L. Willke; Yakun Sophia Shao; Krste Asanovic; Ion Stoica (CGO, 2020)

An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications. - Ckristian Duran; Megan Wachs; Luis E. Rueda G.; Albert Huntington; Javier Ardila; Jack Kang; Andres Amaya; Héctor Gómez; Juan Romero; Laude Fernandez; Felipe Flechas; Rolando Torres; et al. (CICC, 2020)

Invited: Chipyard - An Integrated SoC Research and Implementation Environment. - Alon Amid; David Biancolin; Abraham Gonzalez; Daniel Grubb; Sagar Karandikar; Harrison Liew; Albert Magyar; Howard Mao; Albert J. Ou; Nathan Pemberton; Paul Rigge; Colin Schmidt 001; et al. (DAC, 2020)

Keystone: an open framework for architecting trusted execution environments. - Dayeol Lee; David Kohlbrenner; Shweta Shinde; Krste Asanovic; Dawn Song (EuroSys, 2020)

Genesis: A Hardware Acceleration Framework for Genomic Data Analysis. - Tae Jun Ham; David Bruns-Smith; Brendan Sweeney; Yejin Lee 001; Seong Hoon Seo; U. Gyeong Song; Young H. Oh; Krste Asanovic; Jae W. Lee; Lisa Wu Wills (ISCA, 2020)

AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. - Ameer Haj-Ali; Qijing (Jenny) Huang; William S. Moses; John Xiang; Krste Asanovic; John Wawrzynek; Ion Stoica (MLSys, 2020)

RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization. - Bin Li 018; Yipeng Wang 002; Ren Wang 001; Charlie Tai; Ravi R. Iyer 001; Zhu Zhou; Andrew Herdrich; Tong Zhang; Ameer Haj-Ali; Ion Stoica; Krste Asanovic (NetSoft, 2020)

ProTuner: Tuning Programs with Monte Carlo Tree Search. - Ameer Haj-Ali; Hasan Genc; Qijing Huang 001; William S. Moses; John Wawrzynek; Krste Asanovic; Ion Stoica (CoRR, 2020)

Building Open Trusted Execution Environments. - David Kohlbrenner; Shweta Shinde; Dayeol Lee; Krste Asanovic; Dawn Song (IEEE Secur. Priv., 2020)

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs. - Alon Amid; David Biancolin; Abraham Gonzalez; Daniel Grubb; Sagar Karandikar; Harrison Liew; Albert Magyar; Howard Mao; Albert J. Ou; Nathan Pemberton; Paul Rigge; Colin Schmidt 001; et al. (IEEE Micro, 2020)

A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. - John Charles Wright; Colin Schmidt 001; Ben Keller; Daniel Palmer Dabbelt; Jaehwa Kwak; Vighnesh Iyer; Nandish Mehta; Pi-Feng Chiu; Stevo Bailey; Krste Asanovic; Borivoje Nikolic (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration. - Hasan Genc; Seah Kim; Alon Amid; Ameer Haj-Ali; Vighnesh Iyer; Pranav Prakash; Jerry Zhao; Daniel Grubb; Harrison Liew; Howard Mao; Albert J. Ou; Colin Schmidt 001; et al. (DAC, 2021)

A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET. - Abraham Gonzalez; Jerry Zhao; Ben Korpan; Hasan Genc; Colin Schmidt 001; John Charles Wright; Ayan Biswas; Alon Amid; Farhana Sheikh; Anton Sorokin; Sirisha Kale; Mani Yalamanchi; et al. (ESSCIRC, 2021)

Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs. - Alon Amid; Albert J. Ou; Krste Asanovic; Yakun Sophia Shao; Borivoje Nikolic (ISCAS, 2021)

COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors. - Jerry Zhao; Abraham Gonzalez; Alon Amid; Sagar Karandikar; Krste Asanovic (ISPASS, 2021)

4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. - Colin Schmidt 001; John Charles Wright; Zhongkai Wang; Eric Chang; Albert J. Ou; Woo-Rham Bae; Sean Huang; Anita Flynn; Brian C. Richards; Krste Asanovic; Elad Alon; Borivoje Nikolic (ISSCC, 2021)

A Hardware Accelerator for Protocol Buffers. - Sagar Karandikar; Chris Leary; Chris Kennelly; Jerry Zhao; Dinesh Parimi; Borivoje Nikolic; Krste Asanovic; Parthasarathy Ranganathan (MICRO, 2021)

Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim. - David Biancolin; Albert Magyar; Sagar Karandikar; Alon Amid; Borivoje Nikolic; Jonathan Bachrach; Krste Asanovic (IEEE Micro, 2021)

Accelerating Genomic Data Analytics With Composable Hardware Acceleration Framework. - Tae Jun Ham; Yejin Lee 001; Seong Hoon Seo; U. Gyeong Song; Jae W. Lee; David Bruns-Smith; Brendan Sweeney; Krste Asanovic; Young H. Oh; Lisa Wu Wills (IEEE Micro, 2021)

Cerberus: A Formal Approach to Secure and Efficient Enclave Memory Sharing. - Dayeol Lee; Kevin Cheang; Alexander Thomas; Catherine Lu; Pranav Gaddamadugu; Anjo Vahldiek-Oberwagner; Mona Vij; Dawn Song; Sanjit A. Seshia; Krste Asanovic (CCS, 2022)

Hammer: a modular and reusable physical design flow tool: invited. - Harrison Liew; Daniel Grubb; John Wright; Colin Schmidt 001; Nayiri Krzysztofowicz; Adam M. Izraelevitz; Edward Wang; Krste Asanovic; Jonathan Bachrach; Borivoje Nikolic (DAC, 2022)

Verifying RISC-V Physical Memory Protection. - Kevin Cheang; Cameron Rasmussen; Dayeol Lee; David W. Kohlbrenner; Krste Asanovic; Sanjit A. Seshia (CoRR, 2022)

An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET. - Colin Schmidt 001; John Charles Wright; Zhongkai Wang; Eric Chang; Albert J. Ou; Woorham Bae; Sean Huang; Vladimir M. Milovanovic; Anita Flynn; Brian C. Richards; Krste Asanovic; Elad Alon; et al. (IEEE J. Solid State Circuits, 2022)

MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks. - Seah Kim; Hasan Genc; Vadim Vadimovich Nikiforov; Krste Asanovic; Borivoje Nikolic; Yakun Sophia Shao (HPCA, 2023)

Profiling Hyperscale Big Data Processing. - Abraham Gonzalez; Aasheesh Kolli; Samira Manabi Khan; Sihang Liu 001; Vidushi Dadu; Sagar Karandikar; Jichuan Chang; Krste Asanovic; Parthasarathy Ranganathan (ISCA, 2023)

CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems. - Sagar Karandikar; Aniruddha N. Udipi; Junsun Choi; Joonho Whangbo; Jerry Zhao; Svilen Kanev; Edwin Lim; Jyrki Alakuijala; Vrishab Madduri; Yakun Sophia Shao; Borivoje Nikolic; Krste Asanovic; et al. (ISCA, 2023)

AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads. - Seah Kim; Jerry Zhao; Krste Asanovic; Borivoje Nikolic; Yakun Sophia Shao (MICRO, 2023)

Special Issue on Hot Chips 34. - Ron Diamant; Krste Asanovic (IEEE Micro, 2023)

Zoomie: A Software-like Debugging Tool for FPGAs. - Tianrui Wei; Kevin Laeufer; Katie Lim; Jerry Zhao; Koushik Sen; Jonathan Balkind; Krste Asanovic (ASPLOS (3), 2024)

FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs. - Joonho Whangbo; Edwin Lim; Chengyi Lux Zhang; Kevin Anderson; Abraham Gonzalez; Raghav Gupta; Nivedha Krishnakumar; Sagar Karandikar; Borivoje Nikolic; Yakun Sophia Shao; Krste Asanovic (ISCA, 2024)

Instruction Scheduling in the Saturn Vector Unit. - Jerry Zhao; Daniel Grubb; Miles Rusch; Tianrui Wei; Kevin Anderson; Borivoje Nikolic; Krste Asanovic (CoRR, 2024)

AuRORA: A Full-Stack Solution for Scalable and Virtualized Accelerator Integration. - Seah Kim; Jerry Zhao; Krste Asanovic; Borivoje Nikolic; Yakun Sophia Shao (IEEE Micro, 2024)