Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. - Ondrej Novák; Zdenek Plíva; Jiri Nosek; Andrzej Hlawiczka; Tomasz Garbolino; Krzysztof Gucwa (J. Electron. Test., 2004)

Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. - Tomasz Garbolino; Michal Kopec; Krzysztof Gucwa; Andrzej Hlawiczka (DDECS, 2006)

Test-per-Clock Detection, Localization and Identification of Interconnect Faults. - Michal Kopec; Tomasz Garbolino; Krzysztof Gucwa; Andrzej Hlawiczka (ETS, 2006)

Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. - Tomasz Garbolino; Krzysztof Gucwa; Michal Kopec; Andrzej Hlawiczka (DDECS, 2007)

Interconnect Faults Identification and Localization Using Modified Ring LFSRs. - Andrzej Hlawiczka; Krzysztof Gucwa; Tomasz Garbolino; Michal Kopec (DDECS, 2008)

Effective BIST for crosstalk faults in interconnects. - Tomasz Rudnicki; Tomasz Garbolino; Krzysztof Gucwa; Andrzej Hlawiczka (DDECS, 2009)

How to reduce size of a signature-based diagnostic dictionary used for testing of connections. - Tomasz Garbolino; Krzysztof Gucwa; Andrzej Hlawiczka (DDECS, 2010)

Reduced-size signature-based diagnostic dictionary for interconnection testing. - Tomasz Garbolino; Krzysztof Gucwa; Andrzej Hlawiczka (PDeS, 2010)