A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications. - Meng-Fan Chang; Shu-Meng Yang; Chih-Wei Liang; Chih-Chyuang Chiang; Pi-Feng Chiu; Ku-Feng Lin; Yuan-Hua Chu; Wen-Chin Wu; Hiroyuki Yamauchi (ISSCC, 2010)

Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements. - Meng-Fan Chang; Shu-Meng Yang; Chih-Wei Liang; Chih-Chyuang Chiang; Pi-Feng Chiu; Ku-Feng Lin (IEEE J. Solid State Circuits, 2010)

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. - Shyh-Shyuan Sheu; Meng-Fan Chang; Ku-Feng Lin; Che-Wei Wu; Yu-Sheng Chen; Pi-Feng Chiu; Chia-Chen Kuo; Yih-Shan Yang; Pei-Chia Chiang; Wen-Pin Lin; Che-He Lin; Heng-Yuan Lee; et al. (ISSCC, 2011)

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time. - Meng-Fan Chang; Che-Wei Wu; Chia-Chen Kuo; Shin-Jang Shen; Ku-Feng Lin; Shu-Meng Yang; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih (ISSCC, 2012)

Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology. - Hung-Chang Yu; Kai-Chun Lin; Ku-Feng Lin; Chin-Yi Huang; Yu-Der Chih; Tong-Chern Ong; Tsung-Yung Jonathan Chang; Sreedhar Natarajan; Luan C. Tran (ISSCC, 2013)

A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V. - Hung-Chang Yu; Ku-Feng Lin; Kai-Chun Lin; Yu-Der Chih; Sreedhar Natarajan (VLSI-DAT, 2013)

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes. - Meng-Fan Chang; Shyh-Shyuan Sheu; Ku-Feng Lin; Che-Wei Wu; Chia-Chen Kuo; Pi-Feng Chiu; Yih-Shan Yang; Yu-Sheng Chen; Heng-Yuan Lee; Chen-Hsin Lien; Frederick T. Chen; Keng-Li Su; et al. (IEEE J. Solid State Circuits, 2013)

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro. - Meng-Fan Chang; Che-Wei Wu; Chia-Chen Kuo; Shin-Jang Shen; Sue-Meng Yang; Ku-Feng Lin; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih (IEEE J. Solid State Circuits, 2013)

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Ku-Feng Lin; Yu-Der Chih; Sreedhar Natarajan; Tsung-Yung Jonathan Chang (ISSCC, 2014)

Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chrong Jung Lin; Ku-Feng Lin; Yu-Der Chih; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2015)

Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time. - Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Ku-Feng Lin; Ta-Ching Yeh; Hung-Chang Yu; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2018)

Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $ mu$ A Sensing Resolution, and 17.5-nS Read Access Time. - Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Ku-Feng Lin; Ta-Ching Yeh; Hung-Chang Yu; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2019)

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes. - Ku-Feng Lin; Hiroki Noguchi; Yi-Chun Shih; Perng-Fei Yuh; Yuan-Jen Lee; Tung-Cheng Chang; Sheng-Po Huang; Yu-Fan Lin; Chun-Ying Lee; Yen-Hsiang Huang; Jui-Che Tsai; Saman Adham; et al. (ISSCC, 2024)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)