Routing for chip-package-board co-design considering differential pairs. - Jia-Wei Fang; Kuan-Hsien Ho; Yao-Wen Chang (ICCAD, 2008)

Skew-aware polarity assignment in clock tree. - Po-Yuan Chen; Kuan-Hsien Ho; TingTing Hwang (ACM Trans. Design Autom. Electr. Syst., 2009)

High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. - Xin-Wei Shih; Hsu-Chieh Lee; Kuan-Hsien Ho; Yao-Wen Chang (ICCAD, 2010)

ECO Timing Optimization Using Spare Cells and Technology Remapping. - Kuan-Hsien Ho; Yen-Pin Chen; Jia-Wei Fang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Clock rescheduling for timing engineering change orders. - Kuan-Hsien Ho; Xin-Wei Shih; Jie-Hong R. Jiang (ASP-DAC, 2012)

Constraints on control input and output of polynomial fuzzy systems via a sum of squares approach. - Gwo-Ruey Yu; Kuan-Hsien Ho (FUZZ-IEEE, 2012)

TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. - Kuan-Hsien Ho; Jie-Hong Roland Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

A New Asynchronous Pipeline Template for Power and Performance Optimization. - Kuan-Hsien Ho; Yao-Wen Chang (DAC, 2014)

Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits. - Kuan-Hsien Ho; Hung-Chih Ou; Yao-Wen Chang; Hui-Fang Tsao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Practical Substrate Design Considering Symmetrical and Shielding Routes. - Hao-Yu Chi; Simon Yi-Hung Chen; Hung-Ming Chen; Chien-Nan Liu; Yun-Chih Kuo; Ya-Hsin Chang; Kuan-Hsien Ho (DATE, 2022)