Fabrication Technologies for Three-Dimensional Integrated Circuits (invited). - Rafael Reif; Andy Fan; Kuan-Neng Chen; Shamik Das (ISQED, 2002)

Technology, performance, and computer-aided design of three-dimensional integrated circuits. - Shamik Das; Andy Fan; Kuan-Neng Chen; Chuan Seng Tan; Nisha Checka; Rafael Reif (ISPD, 2004)

Copper wafer bonding in three-dimensional integration. - Kuan-Neng Chen (2005)

Wafer-level 3D integration technology. - Steven J. Koester; Albert M. Young; Roy R. Yu; Sampath Purushothaman; Kuan-Neng Chen; Douglas C. La Tulipe Jr.; Narender Rana; Leathen Shi; Matthew R. Wordeman; Edmund J. Sprogis (IBM J. Res. Dev., 2008)

Wafer-level 3D integration using hybrid bonding. - Cheng-Ta Ko; Kuan-Neng Chen; Wei-Chung Lo; Chuan-An Cheng; Wen-Chun Huang; Zhi-Cheng Hsiao; Huan-Chun Fu; Yu-Hua Chen (3DIC, 2010)

Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network. - Zheng Xu 008; Adam Beece; Dingyou Zhang; Qianwen Chen; Kuan-Neng Chen; Kenneth Rose; Jian-Qiang Lu (3DIC, 2010)

Wafer-level bonding/stacking technology for 3D integration. - Cheng-Ta Ko; Kuan-Neng Chen (Microelectron. Reliab., 2010)

Cu-based bonding technology for 3D integration applications. - Kuan-Neng Chen; Z. Xu; Fei Liu; Cheng-Ta Ko; Chuan-An Cheng; W. C. Huang; H. L. Lin; C. Cabral; Zhi-Cheng Hsiao; N. Klymko; Hsin-Chia Fu; Y. H. Chen; et al. (3DIC, 2011)

Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies. - Cheng-Ta Ko; Zhi-Cheng Hsiao; Y. J. Chang; Peng-Shu Chen; J. H. Huang; Hsin-Chia Fu; Y. J. Huang; C. W. Chiang; W. L. Tsat; Y. H. Chen; Wei-Chung Lo; Kuan-Neng Chen (3DIC, 2011)

Integration schemes and enabling technologies for three-dimensional integrated circuits. - Kuan-Neng Chen; Chuan Seng Tan (IET Comput. Digit. Tech., 2011)

On-chip self-calibrated process-temperature sensor for TSV 3D integration. - Tzu-Ting Chiang; Po-Tsang Huang; Ching-Te Chuang; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Wei Hwang (SoCC, 2012)

Low temperature bonding technology for 3D integration. - Cheng-Ta Ko; Kuan-Neng Chen (Microelectron. Reliab., 2012)

BCB-to-oxide bonding technology for 3D integration. - S. L. Lin; W. C. Huang; C. T. Ko; Kuan-Neng Chen (Microelectron. Reliab., 2012)

Wafer-level Cu-Cu bonding technology. - Ya-Sheng Tang; Yao-Jen Chang; Kuan-Neng Chen (Microelectron. Reliab., 2012)

Low temperature (<180 °C) bonding for 3D integration. - Yan-Pin Huang; Ruoh-Ning Tzeng; Yu-San Chien; Ming-Shaw Shy; Teu-Hua Lin; Kuo-Hua Chen; Ching-Te Chuang; Wei Hwang; Chi-Tsung Chiu; Ho-Ming Tong; Kuan-Neng Chen (3DIC, 2013)

Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. - Teng-Chieh Huang; Po-Tsang Huang; Shang-Lin Wu; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Ching-Te Chuang; Wei Hwang (BioCAS, 2013)

Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. - Ming-Hung Chang; Shang-Yuan Lin; Pei-Chen Wu; Olesya Zakoretska; Ching-Te Chuang; Kuan-Neng Chen; Chen-Chao Wang; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Wei Hwang (ISCAS, 2013)

Through-silicon-via-based double-side integrated microsystem for neural sensing applications. - Chih-Wei Chang; Po-Tsang Huang; Lei-Chun Chou; Shang-Lin Wu; Shih-Wei Lee; Ching-Te Chuang; Kuan-Neng Chen; Jin-Chern Chiou; Wei Hwang; Yen-Chi Lee; Chung-Hsi Wu; Kuo-Hua Chen; et al. (ISSCC, 2013)

Reliability of key technologies in 3D integration. - Cheng-Ta Ko; Kuan-Neng Chen (Microelectron. Reliab., 2013)

Energy-efficient configurable discrete wavelet transform for neural sensing applications. - Tang-Hsuan Wang; Po-Tsang Huang; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Ching-Te Chuang; Wei Hwang (ISCAS, 2014)

18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. - Po-Tsang Huang; Lei-Chun Chou; Teng-Chieh Huang; Shang-Lin Wu; Tang-Shuan Wang; Yu-Rou Lin; Chuan-An Cheng; Wen-Wei Shen; Kuan-Neng Chen; Jin-Chern Chiou; Ching-Te Chuang; Wei Hwang; et al. (ISSCC, 2014)

Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. - Shang-Lin Wu; Po-Tsang Huang; Teng-Chieh Huang; Kuan-Neng Chen; Jin-Chern Chiou; Kuo-Hua Chen; Chi-Tsung Chiu; Ho-Ming Tong; Ching-Te Chuang; Wei Hwang (VLSI-DAT, 2014)

2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. - Po-Tsang Huang; Shang-Lin Wu; Yu-Chieh Huang; Lei-Chun Chou; Teng-Chieh Huang; Tang-Hsuan Wang; Yu-Rou Lin; Chuan-An Cheng; Wen-Wei Shen; Ching-Te Chuang; Kuan-Neng Chen; Jin-Chern Chiou; et al. (IEEE Trans. Biomed. Circuits Syst., 2014)

Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integration. - Chuan-An Cheng; Ryuichi Sugie; Tomoyuki Uchida; Kou-Hua Chen; Chi-Tsung Chiu; Kuan-Neng Chen (3DIC, 2015)

An ultra-fast temporary bonding and release process based on thin photolysis polymer in 3D integration. - Tsung-Yen Tsai; Chien-Hung Lin; Chia-Lin Lee; Shan-Chun Yang; Kuan-Neng Chen (3DIC, 2015)

The influence of device morphology on wafer-level bonding with polymer-coated layer. - Hao-Wen Liang; Hsiu-Chi Chen; Chien-Hung Lin; Chia-Lin Lee; Shan-Chun Yang; Kuan-Neng Chen (3DIC, 2016)

Reliability investigation and mechanism analysis for a novel bonding method of flexible substrate in 3D integration. - Yu-Tao Yang; Yu-Chen Hu; Kuan-Neng Chen (3DIC, 2016)

An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. - Yu-Chieh Huang; Po-Tsang Huang; Shang-Lin Wu; Yu-Chen Hu; Yan-Huei You; Ming Chen; Yan-Yu Huang; Hsiao-Chun Chang; Yen-Han Lin; Jeng-Ren Duann; Tzai-Wen Chiu; Wei Hwang; et al. (ISCAS, 2016)

An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. - Po-Tsang Huang; Yu-Chieh Huang; Shang-Lin Wu; Yu-Chen Hu; Ming-Wei Lu; Ting-Wei Sheng; Fung-Kai Chang; Chun-Pin Lin; Nien-Shang Chang; Hung-Lieh Chen; Chi-Shi Chen; Jeng-Ren Duann; et al. (ISCAS, 2017)

Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. - Yu-Chieh Huang; Po-Tsang Huang; Shang-Lin Wu; Yu-Chen Hu; Yan-Huei You; Ming Chen; Yan-Yu Huang; Hsiao-Chun Chang; Yen-Han Lin; Jeng-Ren Duann; Tzai-Wen Chiu; Wei Hwang; et al. (IEEE Trans. Biomed. Circuits Syst., 2017)

Low-Temperature Wafer-Level Metal Bonding with Gold Thin Film at 100 °C. - Po-Chih Chen; Demin Liu; Kuan-Neng Chen (3DIC, 2019)

Temperature Cycling Reliability of WOW Bumpless Through Silicon Vias. - Chia-Hsuan Lee 003; Hsin-Chi Chang; Jui-Han Liu; Hiroyuki Ito; Young-Suk Kim; Kuan-Neng Chen; Takayuki Ohba (3DIC, 2019)

Low Temperature Cu to Cu Direct Bonding below 150 °C with Au Passivation Layer. - Demin Liu; Po-Chih Chen; Yi-Chieh Tsai; Kuan-Neng Chen (3DIC, 2019)

Investigation of Low Temperature Cu Pillar Eutectic Bonding for 3D Chip Stacking Technology. - Yi-Chieh Tsai; Chia-Hsuan Lee 003; Kuan-Neng Chen (3DIC, 2019)

Room Temperature Cu-Cu Direct Bonding Using Wetting/Passivation Scheme for 3D Integration and Packaging. - Zhong-Jie Hong; Demin Liu; Shu-Ting Hsieh; Han-Wen Hu; Ming-Wei Weng; Chih-I Cho; Jui-Han Liu; Kuan-Neng Chen (VLSI Technology and Circuits, 2022)

An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology. - Jie Zhang; Wei Lu; Po-Tsang Huang; Sih-Han Li; Tsung-Yi Hung; Shih-Hsien Wu; Ming-Ji Dai; I-Shan Chung; Wen-Chao Chen; Chin-Hung Wang; Shyh-Shyuan Sheu; Hung-Ming Chen; et al. (VLSI Technology and Circuits, 2022)

Cost-Effective Low-Temperature Hybrid Bonding Using Layer Transfer Technology. - Yu-Lun Liu 001; Chun-Ta Li; Tzu-Han Sun; Chien-Kang Hsiung; Yuan-Chiu Huang; Kuan-Neng Chen (3DIC, 2024)

Low-Temperature Adhesive Hybrid Bonding Technology with Novel Area-Selective Passivation Layer. - Tzu-Han Sun; Yu-Lun Liu 001; Chun-Ta Li; Wen-Tzu Tsai; Mu-Ping Hsu; Kuan-Neng Chen (3DIC, 2024)

Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. - Wei Lu; Jie Zhang; Yi-Hui Wei; Hsu-Ming Hsiao; Sih-Han Li; Chao-Kai Hsu; Chih-Cheng Hsiao; Feng-Hsiang Lo; Shyh-Shyuan Sheu; Chin-Hung Wang; Wei-Chung Lo; Shih-Chieh Chang; et al. (VLSI Technology and Circuits, 2024)

3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi. - Bo-Jheng Shih; Yu-Ming Pan; Hao-Tung Chung; Chieh-Ling Lee; I-Chun Hsieh; Nein-Chih Lin; Chih-Chao Yang; Po-Tsang Huang; Hung-Ming Chen; Chiao-Yen Wang; Huan-Yu Chiu; Huang-Chung Cheng; et al. (VLSI Technology and Circuits, 2024)