Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic. - Channakeshav; Kuan Zhou; Russell P. Kraft; John F. McDonald 001 (Evolvable Hardware, 2002)

Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques. - Channakeshav; Kuan Zhou; Jong-Ru Guo; Chao You; Bryan S. Goda; Russell P. Kraft; John F. McDonald 001 (FPL, 2002)

Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes. - Kuan Zhou; Channakeshav; Michael Chu; Jong-Ru Guo; S.-C. Liu; Russell P. Kraft; Chao You; John F. McDonald 001 (FPT, 2002)

A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA. - Jong-Ru Guo; Chao You; Michael Chu; Kuan Zhou; Young Uk Yim; Robert W. Heikaus; Russell P. Kraft; John F. McDonald 001 (Engineering of Reconfigurable Systems and Algorithms, 2003)

A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology. - Jong-Ru Guo; Chao You; Kuan Zhou; Bryan S. Goda; Russell P. Kraft; John F. McDonald 001 (FPGA, 2003)

A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme. - Kuan Zhou; Michael Chu; Chao You; Jong-Ru Guo; Channakeshav; John Mayega; John F. McDonald 001; Russell P. Kraft; Bryan S. Goda (FPGA, 2003)

Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory. - Chao You; Jong-Ru Guo; Russell P. Kraft; Michael Chu; Robert W. Heikaus; Okan Erdogan; Peter F. Curran; Bryan S. Goda; Kuan Zhou; John F. McDonald 001 (FPL, 2003)

3D direct vertical interconnect microprocessors test vehicle. - John Mayega; Okan Erdogan; Paul M. Belemjian; Kuan Zhou; John F. McDonald 001; Russell P. Kraft (ACM Great Lakes Symposium on VLSI, 2003)

A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology. - Chao You; Jong-Ru Guo; Russell P. Kraft; Kuan Zhou; Michael Chu; John F. McDonald 001 (ACM Great Lakes Symposium on VLSI, 2003)

The gigahertz FPGA: design consideration and applications. - Jong-Ru Guo; Chao You; Michael Chu; Robert W. Heikaus; Kuan Zhou; Okan Erdogan; Jiedong Diao; Bryan S. Goda; Russell P. Kraft; John F. McDonald 001 (FPGA, 2004)

The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA. - Jong-Ru Guo; Chao You; Peter F. Curran; Michael Chu; Kuan Zhou; Jiedong Diao; A. George; Russell P. Kraft; John F. McDonald 001 (ACM Great Lakes Symposium on VLSI, 2004)

Multi-GHz SiGe design methodologies for reconfigurable computing. - Kuan Zhou; John F. McDonald 001 (ACM Great Lakes Symposium on VLSI, 2005)

A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC. - Jong-Ru Guo; Chao You; Kuan Zhou; Michael Chu; Peter F. Curran; Jiedong Diao; Bryan S. Goda; Russell P. Kraft; John F. McDonald 001 (Integr., 2005)

Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques. - Kuan Zhou; Jong-Ru Guo; Chao You; John Mayega; Russell P. Kraft; T. Zhang; John F. McDonald 001; Bryan S. Goda (J. Circuits Syst. Comput., 2005)

A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block. - Chao You; Jong-Ru Guo; Russell P. Kraft; Michael Chu; Peter F. Curran; Kuan Zhou; Bryan S. Goda; John F. McDonald 001 (Microprocess. Microsystems, 2005)

Triple-rail MOS current mode logic for high-speed self-timed pipeline applications. - Kuan Zhou; Yifei Luo; Sizhong Chen; Allen Drake; John F. McDonald 001; Tong Zhang 002 (ISCAS, 2006)

A picosecond TDC architecture for multiphase PLLs. - Yifei Luo; Gang Chen; Kuan Zhou (ACM Great Lakes Symposium on VLSI, 2009)

Impact of Deep-Trench-Isolation-Sharing Techniques on Ultrahigh-Speed Digital Systems. - Kuan Zhou; John F. McDonald 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 10B 200MHz pipeline ADC with minimal feedback penalty and 0.35pJ/conversion-step. - Gang Chen; Yifei Luo; Jiayin Tian; Kuan Zhou (SoCC, 2010)

Iono-neuromorphic implementation of spike-timing-dependent synaptic plasticity. - Yicong Meng; Kuan Zhou; Joshua J. C. Monzon; Chi-Sang Poon (EMBC, 2011)

On-chip dynamic programming networks using 3D-TSV integration. - Ra'ed Al-Dujaily; Terrence S. T. Mak; Kuan Zhou; Kai-Pui Lam; Yicong Meng; Alexandre Yakovlev; Chi-Sang Poon (ICSAMOS, 2011)

High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology. - Mitchell R. LeRoy; Srikumar Raman; Michael Chu; Jin Woo Kim; Jong-Ru Guo; Kuan Zhou; Chao You; Ryan Clarke; Bryan S. Goda; John F. McDonald 001 (Proc. IEEE, 2015)

Dynamic Block Size Adjustment and Workload Balancing Strategy Based on CPU-GPU Heterogeneous Platform. - Juan Fang; Kuan Zhou; Chen Tan; Hui Zhao 013 (ISPA/BDCloud/SocialCom/SustainCom, 2019)

AAGF: An Efficient Transformer With Mix-Features For Visual Place Recognition. - Kuan Zhou; Zhenyu Xu; Qieshi Zhang; Jun Cheng 002; Ziliang Ren; Xiangyang Gao (ICIP, 2024)