Input assignment algorithm for decoded-PLAs with multi-input decoders. - Kuang-Chien Chen; Saburo Muroga (ICCAD, 1988)

SYLON-DREAM: a multi-level network synthesizer. - Kuang-Chien Chen; Saburo Muroga (ICCAD, 1989)

Timing Optimization for Multi-Level Combinational Networks. - Kuang-Chien Chen; Saburo Muroga (DAC, 1990)

A Resynthesis Approach for Network Optimization. - Kuang-Chien Chen; Yusuke Matsunaga; Saburo Muroga; Masahiro Fujita (DAC, 1991)

Application of Boolean Unification to Combinational Logic Synthesis. - Masahiro Fujita; Yutaka Tamiya; Yuji Kukimoto; Kuang-Chien Chen (ICCAD, 1991)

Concurrent Resynthesis for Network Optimization. - Kuang-Chien Chen; Masahiro Fujita (ICCD, 1991)

Logic synthesis and optimization algorithms - Kuang-Chien Chen (1991)

Efficient Sum-to-One Subsets Algorithm for Logic Optimization. - Kuang-Chien Chen; Masahiro Fujita (DAC, 1992)

Maximal reduction of lookup-table based FPGAs. - Kuang-Chien Chen; Jason Cong (EURO-DAC, 1992)

An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. - Jason Cong; Yuzheng Ding; Andrew B. Kahng; Peter Trajmar; Kuang-Chien Chen (ICCD, 1992)

DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. - Kuang-Chien Chen; Jason Cong; Yuzheng Ding; Andrew B. Kahng; Peter Trajmar (IEEE Des. Test Comput., 1992)

Boolean matching based on Boolean unification. - Kuang-Chien Chen (EURO-DAC, 1993)

A performance driven hierarchical partitioning placement algorithm. - Tong Gao; Chung Laung (Dave) Liu; Kuang-Chien Chen (EURO-DAC, 1993)

LUT-based FPGA technology mapping under arbitrary net-delay models. - Jason Cong; Yuzheng Ding; Tong Gao; Kuang-Chien Chen (Comput. Graph., 1994)

Logic rectification and synthesis for engineering change. - Chih-Chang Lin; David Ihsin Cheng; Malgorzata Marek-Sadowska; Kuang-Chien Chen (ASP-DAC, 1995)

Logic Synthesis for Engineering Change. - Chih-Chang Lin; Kuang-Chien Chen; Shih-Chieh Chang; Malgorzata Marek-Sadowska; Kwang-Ting Cheng (DAC, 1995)

Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. - Anmol Mathur; Kuang-Chien Chen; C. L. Liu 001 (FPGA, 1995)

Cost-free scan: a low-overhead scan path design methodology. - Chih-Chang Lin; Mike Tien-Chien Lee; Malgorzata Marek-Sadowska; Kuang-Chien Chen (ICCAD, 1995)

Re-engineering of timing constrained placements for regular architectures. - Anmol Mathur; Kuang-Chien Chen; C. L. Liu 001 (ICCAD, 1995)

Error Correction Based on Verification Techniques. - Shi-Yu Huang; Kuang-Chien Chen; Kwang-Ting Cheng (DAC, 1996)

Compact Vector Generation for Accurate Power Simulation. - Shi-Yu Huang; Kuang-Chien Chen; Kwang-Ting Cheng; Tien-Chien Lee (DAC, 1996)

Sequential Permissible Functions and their Application to Circuit Optimization. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Kuang-Chien Chen; Mike Tien-Chien Lee (ED&TC, 1996)

On Verifying the Correctness of Retimed Circuits. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen (Great Lakes Symposium on VLSI, 1996)

A novel methodology for transistor-level power estimation. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; Mike Tien-Chien Lee (ISLPED, 1996)

An ATPG-Based Framework for Verifying Sequential Equivalence. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; Uwe Gläser (ITC, 1996)

AQUILA: An equivalence verifier for large sequential circuits. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen (ASP-DAC, 1997)

Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; David Ihsin Cheng (ITC, 1997)

Incremental logic rectification. - Shi-Yu Huang; Kuang-Chien Chen; Kwang-Ting Cheng (VTS, 1997)

Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; Juin-Yeu Joseph Lu (DAC, 1998)

Cost-free scan: a low-overhead scan path design. - Chih-Chang Lin; Malgorzata Marek-Sadowska; Mike Tien-Chien Lee; Kuang-Chien Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

AutoFix: a hybrid tool for automatic logic rectification. - Shi-Yu Huang; Kuang-Chien Chen; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Logic synthesis for engineering change. - Chih-Chang Lin; Kuang-Chien Chen; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

AQUILA: An Equivalence Checking System for Large Sequential Designs. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; Chung-Yang Huang; Forrest Brewer (IEEE Trans. Computers, 2000)

Verifying sequential equivalence using ATPG techniques. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen (ACM Trans. Design Autom. Electr. Syst., 2001)

A Practical Approach to Cycle Bound Estimation for Property Checking. - Chia-Chih Yen; Kuang-Chien Chen; Jing-Yang Jou (IWLS, 2002)

A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. - Chia-Chih Yen; Jing-Yang Jou; Kuang-Chien Chen (IEEE Des. Test Comput., 2004)

An Efficient Sequential SAT Solver With Improved Search Strategies. - Feng Lu 002; Madhu K. Iyer; Ganapathy Parthasarathy; Li-C. Wang; Kwang-Ting Cheng; Kuang-Chien Chen (DATE, 2005)