A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA. - Monk-Ping Leong; Ocean Y. H. Cheung; Kuen Hung Tsoi; Philip Heng Wai Leong (FCCM, 2000)

Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA. - Ocean Y. H. Cheung; Kuen Hung Tsoi; Philip Heng Wai Leong; Monk-Ping Leong (CHES, 2001)

A Massively Parallel RC4 Key Search Engine. - Kuen Hung Tsoi; Kin-Hong Lee; Philip Heng Wai Leong (FCCM, 2002)

Fly - A Modifiable Hardware Compiler. - Chun Hok Ho; Philip Heng Wai Leong; Kuen Hung Tsoi; Ralf Ludewig; Peter Zipf; Alberto García Ortiz; Manfred Glesner (FPL, 2002)

Compact FPGA-based True and Pseudo Random Number Generators. - Kuen Hung Tsoi; Ka Hei Leung; Philip Heng Wai Leong (FCCM, 2003)

An FPGA-based re-configurable 24-bit 96kHz sigma-delta audio DAC. - Ray C. C. Cheung; Kong-Pang Pun; Steve C. L. Yuen; Kuen Hung Tsoi; Philip Heng Wai Leong (FPT, 2003)

Arbitrary function approximation in HDLs with application to the N-body problem. - Chun Hok Ho; Kuen Hung Tsoi; Jackson H. C. Yeung; Yuet Ming Lam; Kin-Hong Lee; Philip Heng Wai Leong; Ralf Ludewig; Peter Zipf; Alberto García Ortiz; Manfred Glesner (FPT, 2003)

An Arithmetic Library and Its Application to the N-body Problem. - Kuen Hung Tsoi; Chun Hok Ho; Jackson H. C. Yeung; Philip Heng Wai Leong (FCCM, 2004)

IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. - Ralf Ludewig; Oliver Soffke; Peter Zipf; Manfred Glesner; Kong-Pang Pun; Kuen Hung Tsoi; Kin-Hong Lee; Philip Heng Wai Leong (FPL, 2004)

Computer Arithmetic Synthesis Technologies on Reconfigurable Platforms. - Kuen Hung Tsoi (FPL, 2005)

Mullet - A Parallel Multiplier Generator. - Kuen Hung Tsoi; Philip Heng Wai Leong (FPL, 2005)

Reconfigurable Acceleration for Monte Carlo Based Financial Simulation. - Guanglie Zhang; Philip Heng Wai Leong; Chun Hok Ho; Kuen Hung Tsoi; Chris C. C. Cheung; Dong-U Lee; Ray C. C. Cheung; Wayne Luk (FPT, 2005)

Field programmable gate array technology for robotics applications. - Philip Heng Wai Leong; Kuen Hung Tsoi (ROBIO, 2005)

High performance physical random number generator. - Kuen Hung Tsoi; Ka Hei Leung; Philip Heng Wai Leong (IET Comput. Digit. Tech., 2007)

A flexible arithmetic system for simulation. - Kuen Hung Tsoi (2007)

Map-reduce as a Programming Model for Custom Computing Machines. - Jackson H. C. Yeung; C. C. Tsang; Kuen Hung Tsoi; Bill S. H. Kwan; Chris C. C. Cheung; Anthony P. C. Chan; Philip Heng Wai Leong (FCCM, 2008)

Axel: a heterogeneous cluster with FPGAs and GPUs. - Kuen Hung Tsoi; Wayne Luk (FPGA, 2010)

Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options. - Anson H. T. Tse; David B. Thomas; Kuen Hung Tsoi; Wayne Luk (FPL, 2010)

Convex models for accelerating applications on FPGA-based clusters. - Qiang Liu 011; Tim Todman; Kuen Hung Tsoi; Wayne Luk (FPT, 2010)

Towards an embedded biologically-inspired machine vision processor. - Vinay Sriram; David D. Cox; Kuen Hung Tsoi; Wayne Luk (FPT, 2010)

Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters. - Anson H. T. Tse; David B. Thomas; Kuen Hung Tsoi; Wayne Luk (FPT, 2010)

Efficient reconfigurable design for pricing asian options. - Anson H. T. Tse; David B. Thomas; Kuen Hung Tsoi; Wayne Luk (SIGARCH Comput. Archit. News, 2010)

Programming framework for clusters with heterogeneous accelerators. - Kuen Hung Tsoi; Anson H. T. Tse; Peter R. Pietzuch; Wayne Luk (SIGARCH Comput. Archit. News, 2010)

FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design. - Yoshiki Yamaguchi; Kuen Hung Tsoi; Wayne Luk (ARC, 2011)

CusComNet: A customisable network for reconfigurable heterogeneous clusters. - Stewart Denholm; Kuen Hung Tsoi; Peter R. Pietzuch; Wayne Luk (ASAP, 2011)

A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only). - Yoshiki Yamaguchi; Kuen Hung Tsoi; Wayne Luk (FPGA, 2011)

Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking. - Xinyu Niu; Kuen Hung Tsoi; Wayne Luk (FPL, 2011)

Power profiling and optimization for heterogeneous multi-core systems. - Kuen Hung Tsoi; Wayne Luk (SIGARCH Comput. Archit. News, 2011)

Efficient Communication for FPGA Clusters. - Stewart Denholm; Kuen Hung Tsoi; Peter R. Pietzuch; Wayne Luk (ARC, 2012)

FPGA based memory efficient high resolution stereo vision system for video tolling. - Yi Shan; Zilong Wang; Wenqiang Wang; Yuchen Hao; Yu Wang 002; Kuen Hung Tsoi; Wayne Luk; Huazhong Yang (FPT, 2012)

Self-Adaptive Heterogeneous Cluster with Wireless Network. - Xinyu Niu; Kuen Hung Tsoi; Wayne Luk (IPDPS Workshops, 2012)

Session types: towards safe and fast reconfigurable programming. - Nicholas Ng; Nobuko Yoshida; Xinyu Niu; Kuen Hung Tsoi (SIGARCH Comput. Archit. News, 2012)

Modelling reconfigurable systems in event driven simulation. - Kuen Hung Tsoi; Tobias Becker; Wayne Luk (SIGARCH Comput. Archit. News, 2012)

Hardware Acceleration of Genetic Sequence Alignment. - James Arram; Kuen Hung Tsoi; Wayne Luk; Peiyong Jiang (ARC, 2013)

Reconfigurable Acceleration of Short Read Mapping. - James Arram; Kuen Hung Tsoi; Wayne Luk; Peiyong Jiang (FCCM, 2013)

Acceleration of real-time Proximity Query for dynamic active constraints. - Thomas C. P. Chau; Ka-Wai Kwok; Gary C. T. Chow; Kuen Hung Tsoi; Kit-Hang Lee; Zion Tse; Peter Y. K. Cheung; Wayne Luk (FPT, 2013)

Parallel neighbourhood search on many-core platforms. - Yuet Ming Lam; Kuen Hung Tsoi; Wayne Luk (Int. J. Comput. Sci. Eng., 2013)

Dimensionality Reduction in Controlling Articulated Snake Robot for Endoscopy Under Dynamic Active Constraints. - Ka-Wai Kwok; Kuen Hung Tsoi; Valentina Vitiello; James Clark 003; Gary C. T. Chow; Wayne Luk; Guang-Zhong Yang (IEEE Trans. Robotics, 2013)

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating. - Assem A. M. Bsoul; Steven J. E. Wilton; Kuen Hung Tsoi; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Custom machine learning architectures: towards realtime anomaly detection for flight testing. - Di Wu; Zhanrui Sun; Yongxin Zhu 001; Li Tian; Hanlin Zhu; Peng Xiong; Zihao Cao; Menglin Wang; Yu Zheng 012; Chao Xiong; Hao Jiang; Kuen Hung Tsoi; et al. (IPDPS Workshops, 2018)

Reconfigurable Hardware Generation for Tensor Flow Models of CNN Algorithms on a Heterogeneous Acceleration Platform. - Jiajun Gao; Yongxin Zhu 001; Meikang Qiu; Kuen Hung Tsoi; Xinyu Niu; Wayne Luk; Ruizhe Zhao; Zhiqiang Que; Wei Mao; Can Feng; Xiaowen Zha; Guobao Deng; et al. (SmartCom, 2018)

Correlation Coefficient Based Cluster Data Preprocessing and LSTM Prediction Model for Time Series Data in Large Aircraft Test Flights. - Hanlin Zhu; Yongxin Zhu 001; Di Wu; Hui Wang 036; Li Tian; Wei Mao; Can Feng; Xiaowen Zha; Guobao Deng; Jiayi Chen; Tao Liu; Xinyu Niu; et al. (SmartCom, 2018)

A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Hongxiang Fan; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Eriko Nurvitadhi; Wayne Luk (FPT, 2020)

On the challenges in programming mixed-precision deep neural networks. - Ruizhe Zhao; Wayne Luk; Chao Xiong; Xinyu Niu; Kuen Hung Tsoi (MAPL@PLDI, 2020)

Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. - Zhiqiang Que; Hiroki Nakahara; Eriko Nurvitadhi; Andrew Boutros; Hongxiang Fan; Chenglong Zeng; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Hongxiang Fan; He Li 008; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Eriko Nurvitadhi; Wayne Luk (ACM Trans. Reconfigurable Technol. Syst., 2023)