A New Method for Assigning Signal Flow Directions to MOS Transistors. - Kuen-Jong Lee; Rajiv Gupta 002; Melvin A. Breuer (ICCAD, 1990)

On the charge sharing problem in CMOS stuck-open fault testing. - Kuen-Jong Lee; Melvin A. Breuer (ITC, 1990)

Constraints for using IDDQ testing to detect CMOS bridging faults. - Kuen-Jong Lee; Melvin A. Breuer (VTS, 1991)

A Fast Testing Method for Sequential Circuits at the State Trasition Level. - Wei-Lun Wang; Jhing-Fa Wang; Kuen-Jong Lee (ITC, 1992)

Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. - Kuen-Jong Lee; Melvin A. Breuer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

SWiTEST: a switch level test generation system for CMOS combinational circuits. - Kuen-Jong Lee; Charles Njinda; Melvin A. Breuer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Built-in intermediate voltage testing for CMOS circuits. - Jing-Jou Tang; Kuen-Jong Lee; Bin-Da Liu (ED&TC, 1995)

A New Architecture for Analog Boundary Scan. - Kuen-Jong Lee; Sheng-Yih Jeng; Tian-Pao Lee (ISCAS, 1995)

An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). - Jing-Jou Tang; Bin-Da Liu; Kuen-Jong Lee (ISCAS, 1995)

An integrated system for assigning signal flow directions to CMOS transistors. - Kuen-Jong Lee; Chih-Nan Wang; Rajiv Gupta 002; Melvin A. Breuer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A practical current sensing technique for IDDQ testing. - Jing-Jou Tang; Kuen-Jong Lee; Bin-Da Liu (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. - Kuen-Jong Lee; Jing-Jou Tang (Asian Test Symposium, 1996)

Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. - Kuen-Jong Lee; Jing-Jou Tang; Tsung-Chu Huang; Cheng-Liang Tsai (Asian Test Symposium, 1996)

Built-in current sensor designs based on the bulk-driven technique. - Tsung-Chu Huang; Min-Cheng Huang; Kuen-Jong Lee (Asian Test Symposium, 1997)

On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation. - Kuen-Jong Lee; Jing-Jou Tang; Wern-Yih Duh (Asian Test Symposium, 1998)

Using a single input to support multiple scan chains. - Kuen-Jong Lee; Jih-Jeen Chen; Cheng-Hua Huang (ICCAD, 1998)

Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters. - Kuen-Jong Lee; Cheng-Hsuing Kuo (J. Inf. Sci. Eng., 1998)

A General Structure of Feedback Shift Registers for Built-In Self Test. - Kuen-Jong Lee; Wei-Lun Wang; Jhing-Fa Wang (J. Inf. Sci. Eng., 1998)

A graph representation for programmable logic arrays to facilitate testing and logic design. - Jing-Jou Tang; Kuen-Jong Lee; Bin-Da Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

An Input Control Technique for Power Reduction in Scan Circuits During Test Application. - Tsung-Chu Huang; Kuen-Jong Lee (Asian Test Symposium, 1999)

An Efficient BIST Method for Small Buffers. - Wen-Ben Jone; Der-Cheng Huang; S. C. Wu; Kuen-Jong Lee (VTS, 1999)

Broadcasting test patterns to multiple circuits. - Kuen-Jong Lee; Jih-Jeen Chen; Cheng-Hua Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. - Kuen-Jong Lee; Jing-Jou Tang; Tsung-Chu Huang (ACM Trans. Design Autom. Electr. Syst., 1999)

A hierarchical test control architecture for core based design. - Kuen-Jong Lee; Cheng-I Huang (Asian Test Symposium, 2000)

Peak-power reduction for multiple-scan circuits during test application. - Kuen-Jong Lee; Tsung-Chu Huang; Jih-Jeen Chen (Asian Test Symposium, 2000)

Accelerated test pattern generators for mixed-mode BIST environments. - Wei-Lun Wang; Kuen-Jong Lee (Asian Test Symposium, 2000)

An on Chip ADC Test Structure. - Yun-Che Wen; Kuen-Jong Lee (DATE, 2000)

A Low-Power LFSR Architecture. - Tsung-Chu Huang; Kuen-Jong Lee (Asian Test Symposium, 2001)

A token scan architecture for low power testing. - Tsung-Chu Huang; Kuen-Jong Lee (ITC, 2001)

Reduction of power consumption in scan-based circuits during testapplication by an input control technique. - Tsung-Chu Huang; Kuen-Jong Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Analysis and generation of control and observation structures foranalog circuits. - Yun-Che Wen; Kuen-Jong Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

An on-chip march pattern generator for testing embedded memory cores. - Wei-Lun Wang; Kuen-Jong Lee; Jhing-Fa Wang (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. - Kuen-Jong Lee; Jih-Jeen Chen (Asian Test Symposium, 2002)

An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. - Kuen-Jong Lee; Tsung-Chu Huang (J. Electron. Test., 2002)

Guest Editorial. - Kuen-Jong Lee; Chau-Chin Su (J. Electron. Test., 2002)

An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. - Wei-Lun Wang; Kuen-Jong Lee (J. Electron. Test., 2002)

An efficient BIST method for distributed small buffers. - Wen-Ben Jone; Der-Cheng Huang; S. C. Wu; Kuen-Jong Lee (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. - Kuen-Jong Lee; Soon-Jyh Chang; Ruei-Shiuan Tzeng (Asian Test Symposium, 2003)

Test pattern generation and clock disabling for simultaneous test time and power reduction. - Jih-Jeen Chen; Chia-Kai Yang; Kuen-Jong Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. - Chih-Haur Huang; Kuen-Jong Lee; Soon-Jyh Chang (Asian Test Symposium, 2004)

Test Power Reduction with Multiple Capture Orders. - Kuen-Jong Lee; Shaing-Jer Hsu; Chia-Ming Ho (Asian Test Symposium, 2004)

An embedded processor based SOC test platform. - Kuen-Jong Lee; Chia-Yi Chu; Yu-Ting Hong (ISCAS (3), 2005)

A novel test methodology based on error-rate to support error-tolerance. - Kuen-Jong Lee; Tong-Yu Hsieh; Melvin A. Breuer (ITC, 2005)

A high speed BIST architecture for DDR-SDRAM testing. - Sheng-Chih Shen; Hung-Ming Hsu; Yi-Wei Chang; Kuen-Jong Lee (MTDT, 2005)

A complete memory address generator for scan based March algorithms. - Wei-Lun Wang; Kuen-Jong Lee (MTDT, 2005)

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. - Chun-Ming Huang; Kuen-Jong Lee; Chih-Chyau Yang; Wen-Hsiang Hu; Shi-Shen Wang; Jeng-Bin Chen; Chi-Shi Chen; Lan-Da Van; Chien-Ming Wu; Wei-Chang Tsai; Jing-Yang Jou (SoCC, 2006)

An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. - Tong-Yu Hsieh; Kuen-Jong Lee; Melvin A. Breuer (VTS, 2006)

Test Efficiency Analysis and Improvement of SOC Test Platforms. - Tong-Yu Hsieh; Kuen-Jong Lee; Jian-Jhih You (ATS, 2007)

Reduction of detected acceptable faults for yield improvement via error-tolerance. - Tong-Yu Hsieh; Kuen-Jong Lee; Melvin A. Breuer (DATE, 2007)

A Software-Based Test Methodology for Direct-Mapped Data Cache. - Yi-Cheng Lin; Yi-Ying Tsai; Kuen-Jong Lee; Cheng-Wei Yen; Chung-Ho Chen (ATS, 2008)

A hybrid self-testing methodology of processor cores. - Tai-Hua Lu; Chung-Ho Chen; Kuen-Jong Lee (ISCAS, 2008)

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. - Laung-Terng Wang; Ravi Apte; Shianling Wu; Boryau Sheu; Kuen-Jong Lee; Xiaoqing Wen; Wen-Ben Jone; Chia-Hsien Yeh; Wei-Shin Wang; Hao-Jan Chao; Jianghao Guo; Jinsong Liu; et al. (ITC, 2008)

A hybrid software-based self-testing methodology for embedded processor. - Tai-Hua Lu; Chung-Ho Chen; Kuen-Jong Lee (SAC, 2008)

An Error Rate Based Test Methodology to Support Error-Tolerance. - Tong-Yu Hsieh; Kuen-Jong Lee; Melvin A. Breuer (IEEE Trans. Reliab., 2008)

Full System Simulation and Verification Framework. - Jing-Wun Lin; Chen-Chieh Wang; Chin-Yao Chang; Chung-Ho Chen; Kuen-Jong Lee; Yuan-Hua Chu; Jen-Chieh Yeh; Ying-Chuan Hsiao (IAS, 2009)

Transaction Level Modeling and Design Space Exploration for SOC Test Architectures. - Chin-Yao Chang; Chih-Yuan Hsiao; Kuen-Jong Lee; Alan P. Su (Asian Test Symposium, 2009)

Tolerance of performance degrading faults for effective yield improvement. - Tong-Yu Hsieh; Melvin A. Breuer; Murali Annavaram; Sandeep K. Gupta 001; Kuen-Jong Lee (ITC, 2009)

A low-cost SOC debug platform based on on-chip test architectures. - Kuen-Jong Lee; Si-Yuan Liang; Alan P. Su (SoCC, 2009)

Turbo1500: Core-Based Design for Test and Diagnosis. - Laung-Terng Wang; Ravi Apte; Shianling Wu; Boryau Sheu; Wen-Ben Jone; Jianghao Guo; Kuen-Jong Lee; Wei-Shin Wang; Xiaoqing Wen; Hao-Jan Chao; Jinsong Liu; Yanlong Niu; et al. (IEEE Des. Test Comput., 2009)

A Complete Logic BIST Technology with No Storage Requirement. - Wei-Cheng Lien; Kuen-Jong Lee (Asian Test Symposium, 2010)

On-Chip SOC Test Platform Design Based on IEEE 1500 Standard. - Kuen-Jong Lee; Tong-Yu Hsieh; Chin-Yao Chang; Yu-Ting Hong; Wen-Cheng Huang (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A software/hardware co-debug platform for multi-core systems. - Kuen-Jong Lee; Alan P. Su; Long-Feng Chen; Jia-Wei Jhou; Jiff Kuo; Mark Liu (ASICON, 2011)

EPIDETOX: an ESL platform for integrated circuit design and tool exploration. - Kuen-Jong Lee; Chin-Yao Chang; I-Jou Chen (CODES+ISSS, 2011)

An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. - Tong-Yu Hsieh; Kuen-Jong Lee; Melvin A. Breuer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Test Response Compaction via Output Bit Selection. - Kuen-Jong Lee; Wei-Cheng Lien; Tong-Yu Hsieh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Programmable System-on-Chip for Silicon Prototyping. - Chun-Ming Huang; Chien-Ming Wu; Chih-Chyau Yang; Shih-Lun Chen; Chi-Shi Chen; Jiann-Jenn Wang; Kuen-Jong Lee; Chin-Long Wey (IEEE Trans. Ind. Electron., 2011)

Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores. - Tai-Hua Lu; Chung-Ho Chen; Kuen-Jong Lee (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume. - Wei-Cheng Lien; Kuen-Jong Lee; Tong-Yu Hsieh (Asian Test Symposium, 2012)

Accumulator-based output selection for test response compaction. - Wei-Cheng Lien; Kuen-Jong Lee; Tong-Yu Hsieh; Shih-Shiun Chien; Krishnendu Chakrabarty (ISCAS, 2012)

Routing-efficient implementation of an internal-response-based BIST architecture. - Wei-Cheng Lien; Tong-Yu Hsieh; Kuen-Jong Lee (VLSI-DAT, 2012)

Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. - Kuen-Jong Lee; Tong-Yu Hsieh; Melvin A. Breuer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

A New LFSR Reseeding Scheme via Internal Response Feedback. - Wei-Cheng Lien; Kuen-Jong Lee; Tong-Yu Hsieh; Krishnendu Chakrabarty (Asian Test Symposium, 2013)

An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip. - Kuen-Jong Lee; Chin-Yao Chang; Hung-Yang Yang (VLSI-DAT, 2013)

An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters. - Wei-Cheng Lien; Kuen-Jong Lee; Tong-Yu Hsieh; Wee-Lung Ang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Counter-Based Output Selection for Test Response Compaction. - Wei-Cheng Lien; Kuen-Jong Lee; Tong-Yu Hsieh; Krishnendu Chakrabarty; Yu-Hua Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults. - Cheng-Hung Wu; Kuen-Jong Lee (ATS, 2014)

Output-bit selection with X-avoidance using multiple counters for test-response compaction. - Wei-Cheng Lien; Kuen-Jong Lee; Krishnendu Chakrabarty; Tong-Yu Hsieh (ETS, 2014)

An efficient diagnosis-aware pattern generation procedure for transition faults. - Kuen-Jong Lee; Cheng-Hung Wu (ITC, 2014)

Output selection for test response compaction based on multiple counters. - Wei-Cheng Lien; Kuen-Jong Lee; Krishnendu Chakrabarty; Tong-Yu Hsieh (VLSI-DAT, 2014)

An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model. - Cheng-Hung Wu; Kuen-Jong Lee; Wei-Cheng Lien (VTS, 2014)

Efficient LFSR Reseeding Based on Internal-Response Feedback. - Wei-Cheng Lien; Kuen-Jong Lee; Tong-Yu Hsieh; Krishnendu Chakrabarty (J. Electron. Test., 2014)

Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing. - Yi-Hua Li; Wei-Cheng Lien; Ing-Chao Lin; Kuen-Jong Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions. - Chin-Yao Chang; Kuen-Jong Lee (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Distinguishing dynamic bridging faults and transition delay faults. - Cheng-Hung Wu; Saint James Lee; Kuen-Jong Lee (ASICON, 2015)

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. - Liang-Che Li; Wen-Hsuan Hsu; Kuen-Jong Lee; Chun-Lung Hsu (ASP-DAC, 2015)

A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC. - Hsin-Chen Chen; Cheng-Rong Wu; Katherine Shu-Min Li; Kuen-Jong Lee (DATE, 2015)

Improve transition fault diagnosability via observation point insertion. - Cheng-Hung Wu; Yi-Da Wang; Kuen-Jong Lee (VLSI-DAT, 2015)

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. - Liang-Ying Lu; Ching-Yao Chang; Zhao-Hong Chen; Bo-Ting Yeh; Tai-Hua Lu; Peng-Yu Chen; Pin-Hao Tang; Kuen-Jong Lee; Lih-Yih Chiou; Soon-Jyh Chang; Chien-Hung Tsai; Chung-Ho Chen; et al. (ASP-DAC, 2016)

Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults. - Cheng-Hung Wu; Saint James Lee; Kuen-Jong Lee (ASP-DAC, 2016)

Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis. - Sheng-Lin Lin; Cheng-Hung Wu; Kuen-Jong Lee (ATS, 2016)

Autonomous Testing for 3D-ICs with IEEE Std. 1687. - Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee; Hans-Joachim Wunderlich (ATS, 2016)

An on-chip self-test architecture with test patterns recorded in scan chains. - Kuen-Jong Lee; Pin-Hao Tang; Michael A. Kochte (ITC, 2016)

Output bit selection methodology for test response compaction. - Wei-Cheng Lien; Kuen-Jong Lee (ITC, 2016)

Transformation of multiple fault models to a unified model for ATPG efficiency enhancement. - Cheng-Hung Wu; Kuen-Jong Lee (ITC, 2016)

Test Compression with Single-Input Data Spreader and Multiple Test Sessions. - Chang-Wen Chen; Yi-Cheng Kong; Kuen-Jong Lee (ATS, 2017)

A run-pause-resume silicon debug technique for multiple clock domain systems. - Shuo-Lian Hong; Kuen-Jong Lee (ITC-Asia, 2017)

Test generation for open and delay faults in CMOS circuits. - Cheng-Hung Wu; Kuen-Jong Lee; Sudhakar M. Reddy (ITC-Asia, 2017)

A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems. - Shuo-Lian Hong; Kuen-Jong Lee (ITC, 2017)

A low power synthesis flow for multi-rate systems. - Hsin-Pang Kuo; Alan P. Su; Kuen-Jong Lee (VLSI-DAT, 2017)

Test Stimulus Compression Based on Broadcast Scan With One Single Input. - Jhen-Zong Chen; Kuen-Jong Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges. - Wen-Hsuan Hsu; Michael Andreas Kochte; Kuen-Jong Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks. - Chia-Chi Wu; Man-Hsuan Kuo; Kuen-Jong Lee (ATS, 2018)

Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run. - Yi-Cheng Kung; Kuen-Jong Lee; Sudhakar M. Reddy (ITC-Asia, 2018)

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. - Yi-Cheng Kung; Kuen-Jong Lee; Sudhakar M. Reddy (ITC, 2018)

A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip. - Chun-Wei Wu; Kuen-Jong Lee; Alan P. Su (IEEE Trans. Computers, 2018)

A Repair-for-Diagnosis Methodology for Logic Circuits. - Cheng-Hung Wu; Sheng-Lin Lin; Kuen-Jong Lee; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Using Unstable SRAM Bits for Physical Unclonable Function Applications on Off-The-Shelf SRAM. - Zhi-Wei Lai; Kuen-Jong Lee (APCCAS, 2019)

Deep Learning Based Test Compression Analyzer. - Cheng-Hung Wu; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Gaurav Veda; Sudhakar M. Reddy; Chun-Cheng Hu; Chong-Siao Ye (ATS, 2019)

Time-Related Hardware Trojan Attacks on Processor Cores. - Man-Hsuan Kuo; Chun-Ming Hu; Kuen-Jong Lee (ITC-Asia, 2019)

International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia. - Kuen-Jong Lee; Shi-Yu Huang; Huawei Li; Tomoo Inoue; Yervant Zorian (ITC, 2019)

A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model. - Chao-Jun Shang; Cheng-Hung Wu; Kuen-Jong Lee; Yu-Hsiang Chen (VLSI-DAT, 2019)

On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains. - Kuen-Jong Lee; Bo-Ren Chen; Michael Andreas Kochte (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction. - Cheng-Hung Wu; Kuen-Jong Lee; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Efficient Prognostication of Pattern Count with Different Input Compression Ratios. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski (ETS, 2020)

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Shi-Xuan Zheng (ITC-Asia, 2020)

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. - Fong-Jyun Tsai; Chong-Siao Ye; Kuen-Jong Lee; Shi-Xuan Zheng; Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Chen Wang 014; Justyna Zawada (ITC, 2020)

Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run. - Yi-Cheng Kung; Kuen-Jong Lee; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Lightweight Hardware-Based Memory Protection Mechanism on IoT Processors. - Hung-Yao Chi; Kuen-Jong Lee; Tzu-Chun Jao (ATS, 2021)

Test Chips With Scan-Based Logic Arrays. - Yu-Hsiang Chen; Chia-Ming Hsu; Kuen-Jong Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

An Authentication-Based Secure IJTAG Network. - Shih-Chun Yeh; Kuen-Jong Lee; Dong-Yi Chen (ATS, 2022)

Diagnosing Transition Delay Faults under Scan-Based Logic Array. - Duo-Yao Kang; Shiou-Ning Lin; Kuen-Jong Lee (ITC-Asia, 2022)

Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks. - Yan-Fu Chen; Duo-Yao Kang; Kuen-Jong Lee (ITC, 2022)

Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. - Shi-Xuan Zheng; Chung-Yu Yeh; Kuen-Jong Lee; Chen Wang 014; Wu-Tung Cheng; Mark Kassab; Janusz Rajski; Sudhakar M. Reddy (VTS, 2022)

A Secure JTAG Wrapper for SoC Testing and Debugging. - Kuen-Jong Lee; Zheng-Yao Lu; Shih-Chun Yeh (IEEE Access, 2022)

Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function. - Zhi-Wei Lai; Po-Hua Huang; Kuen-Jong Lee (J. Electron. Test., 2022)

An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults. - Kuen-Jong Lee; Cheng-Hung Wu; Tsung-Yu Hou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Efficient Test Compression Configuration Selection. - Chong-Siao Ye; Shi-Xuan Zheng; Fong-Jyun Tsai; Chen Wang 014; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Justyna Zawada; Mark Kassab; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Dynamic-Key Based Secure Scan Architecture for Manufacturing and In-Field IC Testing. - Kuen-Jong Lee; Ching-An Liu; Chia-Chi Wu (IEEE Trans. Emerg. Top. Comput., 2022)

An On-chip High-resolution Delay Measurement Scheme for TSVs in 3DIC. - Dong-Yi Chen; Cheng-Hong Lee; Kuen-Jong Lee; Nan-Hsin Tseng; Hsin-Wei Hung; Hao-Yu Yang (APCCAS, 2024)

A Lightweight Memory Protection Scheme with Criticality-Aware Encryption and Embedded MAC for Secure DNN Accelerators. - Yu-Chuan Lin; Kuen-Jong Lee (APCCAS, 2024)

A Universal Sequential Authentication Scheme for TAPC-Based Test Standards. - Guan-Rong Chen; Kuen-Jong Lee (IEEE Trans. Very Large Scale Integr. Syst., 2025)